Verilog Synthesis: Reg vs Reg+Wire for Module Instantiation

0
votes

I am fairly new to Verilog and FPGA development and have noticed that there are various differences you have to be aware of between simulation and synthesis. I am using the Altera DE1 board with Quartus II Software.

Here is something I cannot figure out. I have code as follows to instantiate a module:

reg [9:0] x0;
initial begin
    x0 = 10'd200;
end

linepro linedrawer1 
     (.CLOCK(I_CLK),
     .RST(reset_drawer),
      .done(drawer_done),
     .x0(x0), 
     .y0(10'd200), 
     .x1(10'd500), 
     .y1(10'd100), 
     .outx(x), 
     .outy(y));

As you can see, I am hooking an initialized reg directly to the port of my linepro module. This code appears to work under simulation, but does NOT correctly initialize x0 on the fpga board.

To make this code work properly, and the linepro module be instantiated correctly, I make the following slight modification:

reg [9:0] x0reg;
wire [9:0] x0;
assign x0=x0reg;
initial begin
    x0reg = 10'd200;
end

linepro linedrawer1 
     (.CLOCK(I_CLK),
     .RST(reset_drawer),
      .done(drawer_done),
     .x0(x0), 
     .y0(10'd200), 
     .x1(10'd500), 
     .y1(10'd100), 
     .outx(x), 
     .outy(y));

In this example, I assign the reg to a wire and hook the wire into the linepro module.

What is the difference, if any, between using a reg directly to instantiate a module and assigning a reg to a wire and using that wire to instantiate the module? What are some reasons one method might work and the other might not?

Thanks in advance for any assistance.

2
verilogfpga
Is the x0 port on linepro an input or output? – user1902824
It's an input declared as follows: input [9:0] x0 – vancan1ty
What do you mean by " but does NOT correctly initialize x0 on the fpga board."? If you mean it is not initialized to 200, it's because the initial blocks are not synthesizable. – Eugene Sh.
As much as I dislike it initial blocks are an accepted way of setting defaults for FPGA. they are not synthesizable for ASIC. The Second example uses initial and it does synthesis. – Morgan

2 Answers

2
votes

When you are writing synthesize RTL, you should keep in mind is what logic circuits are you actually trying to implement. While in general initial blocks are not synthesizable, some FPGA vendors will allow you to specify the power on state for memory elements such as flip-flops, latches, and memories. In this case, it doesn't look like x0 is any of those things--it's merely a constant being applied to one input of your linepro module. In that case, you should probably simply specify that value in the port list as you did with the y0, y1, and x1 ports, which is completely synthesizable, rather than using an initial block.

0
votes

Quartus does support initialization for both registers and memories using the "initial" statement. I suspect the issue here is that you never actually implement the register.

I wonder if this would work:

reg [9:0] x0reg;
initial x0reg = 10'd200;
always @(posedge clk) begin
  x0reg <= x0reg;
end

This should infer an x0reg register, and initialize it to 0x200 when the FPGA gets configured. Alternately, if you just want reg to behave like a wire:

reg [9:0] x0reg;
always_comb x0_reg = 10'd200;

The above should work. Note that always @* will not work in that context, as one of the key differences between always @* and always_comb is that always_comb blocks get triggered at the beginning of simulation, while always @* blocks only get triggered if an input changes (which might not occur at time zero). (Generally, you should always use always_comb and never use always @*.)