Verilog: multidimensional registered outputs

Question

I have some Verilog module with multidimensional outputs (to 7-segment LED panels of my DE1-SoC). I want to make the outputs registered. To test it, I give some dummy code to one of LED digits. Its RTL simulation passes OK, it's even compiled by Quartus, but actually it does not work.

module Top
(
    input CLK50,
    output [6:0] HEX[5:0]
);

reg[6:0] hex_regs[5:0];

//assign HEX[0][6:0] = 7'b010_1010; //if use assign, it assigns value to output, but I want it registered

initial
begin
    hex_regs[5][6:0] = 7'b101_0101;
end

assign HEX = hex_regs;

endmodule

Cannot you tell me, how to do this correctly and where is my mistake?

Morgan Morgan · Accepted Answer · 2015-01-06T14:39:18

As you said the posted code simulates fine (on EDA Playground), but multidimensional ports were supported after the ANSI style port lists so I would recommend putting reg in the port list.

module Top
(
    input            CLK50,
    output reg [6:0] HEX   [5:0]
);

It is a relatively new feature and while supported by the simulator may not be part of the synthesis tool. I think it was introduced in the 2009 SystemVerilog LRM.

At least ensure that your toolset supports this version of the language and that it is interpreting them as system verilog files, by file extension .sv or with the command line -sv flag.

I have tried this before and at the time ran into issues with the way the sysnthesis tool was unpacking and repacking the arrays, the bits all got connected the wrong way around.

One work around mentioned on EDA board involves packing and unpacking them each side of the port.

module top (in, out);
  input   [31:0] in;
  wire     [7:0] array [0:3];
  output  [31:0] out;

  assign {array[3],array[2],array[1],array[0]} = in;
  assign out = {array[3],array[2],array[1],array[0]};
endmodule

Verilog: multidimensional registered outputs

1 Answers