verilog module renaming using precompiler

Question

I want to name a module using a `define directive

It seems to work if I use a macro like :

`define module_rename(NAME,TAG) ``NAME``TAG

module `module_rename(foo,_A) (...);

but it fails (in quartus) if I do the following :

`define NAME foo
`define TAG _A

module `NAME`TAG (...);

Syntax Error near_A missing";"

Any idea what is wrong ?

Tx for your help

dave_59 dave_59 · Accepted Answer · 2021-01-18T16:09:19

The SystemVerilog token pasting operator `` is only allowed in the body of a `define text macro, and that is the only place you can join text together to form a single identifier. The second example you wrote is seen as illegal syntax.

module foo _A;

verilog module renaming using precompiler

1 Answers