System Verilog Variable Module Name

Question

Is it possible to have variable module name which could then be picked by some parameter? I am looking for the syntax for if...else inside a macro definition.

module test;

  `define NAME(x) if (x == 0) mod_e else mod_w
  generate
    for (genvar i = 0; i < 2; i++) begin
      `NAME(i) inst_name (.a(a),.b(b),...);
    end
  endgenerate

endmodule

One way is to do it like below, but it requires connecting all ports 2 times, which is inconvenient for modules with hundreds of IOs and prone to errors.

module test;

  generate
    if (SOME_PARAM == 0) begin
      mod_e inst_name (.a(a),.b(b),...);
    end else begin
      mod_w inst_name (.a(a),.b(b),...);
    end
  endgenerate

endmodule

There's some expression evaluation happening in the port list and the names don't match. I didn't show it here. — Wilderness

Serge Serge · Accepted Answer · 2020-05-07T01:26:07

As a possible solution to your hundreds of ports issues, assuming that all instances have the same set of ports, you can approach this problem differently, by defining an instance macro:

`define INST(mod_name) mod_name inst_name(.a(a), .b(b), ...);

if(SOME_PARAM == 0)
   `INST(mod_e)
else
   `INST(mod_w)

System Verilog Variable Module Name

2 Answers