System verilog/verilog ---events

Question

task monitorPush();
  begin
    bit [7:0] data = 0;
    while (1) begin
      @ (posedge intf.clk);
      if (intf.cb.wr_cs== 1 &&  intf.cb.wr_en== 1) begin
        // @ (posedge intf.clk);
        data = intf.data_in;
        sb.addItem(data);
        $write("%dns : Write posting to scoreboard data = %x\n",$time, data);
      end
    end
  end
  endtask

How is the above code different from below code? As in how does shifting posedge clock from line 5 to 7 change the code? Thanks in advance

task monitorPush();
  begin
    bit [7:0] data = 0;
    while (1) begin
      // @ (posedge intf.clk);
      if (intf.cb.wr_cs== 1 &&  intf.cb.wr_en== 1) begin
        @ (posedge intf.clk);
        data = intf.data_in;
        sb.addItem(data);
        $write("%dns : Write posting to scoreboard data = %x\n",$time, data);
      end
    end
  end
endtask

Answer 1

The @(posedge intf.clk) waits for the posedge of the clk then continues execution.

Version 1 of your code waits for a clk (posedge) then performs the if statement.

Version 2: In the case of the failing if statement will execute continuously, inside the while true block, until the if becomes true then you will wait for the clk posedge.

Answer 2

In Version 2 you have the possibility of being stuck in a infinite loop because the simulator will get stuck evaluating the while loop and the if statement and won't switch to executing other parts of your code. In Version 1 the @(posedge intf.clk) will let the simulator jump to other parts of the code. In short, go with Version 1.

Answer 3

Version 2) will hang your simulation because you don't have an else condition for the if. From the moment the monitor function is called and the first encounter of wr_cs/wr_en being zero will get stuck in the while(1) infinite loop as there is no else condition nor any timing event.

Version 1 is the right way to use. Most of the times your control and data signals change with respect to clock.

In Version 1), you will sample the data for score board on the clock edge when the CS/WEN goes high

In version 2), you will sample the data one clock after the wr_cs/wr_en goes high.(as you wait for clock after seeing them high) You might end up getting a wrong data.