Xilinx FIFO IP block output in simulation

Question

I was playing around with Xilinx FIFO IP block and there are some things that I cannot explain in the following output :

Test Bench code :

`define wrclk_period 20 ;
`define rdclk_period 10 ;

module testbench;
reg rst;
reg wr_clk ;
reg rd_clk ;
reg [7:0] din ; 
reg wr_en ;
reg rd_en ;
wire [7:0] dout ;
wire full ; 
wire empty ;

fifo_generator_0 FG0(rst,wr_clk,rd_clk,din,wr_en,rd_en,dout,full,empty) ;


initial wr_clk = 1 ;
always #10 wr_clk = ~wr_clk ;

initial rd_clk = 1 ;
always #5 rd_clk = ~rd_clk ;




integer i,j ;

initial begin 
rst = 1 ; 
#10
   din = 0 ;
   wr_en = 0 ;
   rd_en = 0 ;
   rst = 0 ;
   #`wrclk_period ;
   rst = 1 ;
   #`wrclk_period ;
   rst = 0 ;
   #60;


   for(i= 0 ; i<=5 ; i = i+1  ) begin 
     wr_en = 1 ;
     din = i ;
     #`wrclk_period ;
   end 

   wr_en = 0 ;
   #`wrclk_period ;

   #`rdclk_period ;

   for( j= 0 ; j<=5 ; j = j+1  ) begin 
        rd_en = 1 ;
        #`rdclk_period ;
    end

      rd_en = 0 ;
      #`rdclk_period ;

      $stop ;
   end
endmodule

1) Question 1: The output variable full is high in the beginning . Why is this the case ?

2) Question 2 : Why do we miss the data 1 in the dout ? I can see 2,3,4,5 but 1 does not show up .

3) After rd_en is set to 1 , the dout change from 3 to 4 takes 2 clock cycles while the change from 2 to 3 happens at the immediate next posedge of the read clock ?

Oldfart Oldfart · Accepted Answer · 2019-01-04T11:10:21

Sorry had this in a comment but ran heavily out of space.

I am not familiar wit the IP but can make some educated guesses.

1/ I suspect you have to wait longer after a reset before you start using the FIFO. Maybe by that time the full flag is low.
The problem with the 'full' flag may be because after the reset the FIFO level has to pass the clock domain crossing which takes a few cycles. As a precaution the designer set it to 'full' as that is the fail safe state.

2/ I also suspect the value 0x01 is not written because the FIFO still thinks it is full.

3/ Study the waveform more carefully: 2->3 is one clock, 3->4 is one clock but then you are reading when the FIFO is empty!! Thus 5 comes out only after the FIFO is no longer empty.

In general if you test a block like this for the first time, make your timings are a lot longer. So wait longer after the reset before writing, wait longer after the writing before reading.

Last comment: Your rd_en seem to run of the rising edge of the rd_clk fine, no problem. But the your wr_en signal is running of the falling edge of the wr_clk or of the rising edge of rd_clk. If it is the latter it is wrong!

Xilinx FIFO IP block output in simulation

1 Answers