simulation errors in implementing xilinx fifo core

Question

I have generated a core IP from Xilinx core generator for FIFO. I get some errors while simulating the design.

In stimulus my clock switches on every #1 and write flag is also set at #1 followed by din and again write flag unset at #1. Followed by same thing with read flag

The problems are: 1. Full flag is set earlier than the data is filled with FIFO. 2. The read won't start from first pointer, instead starts with 4th read pointer.

Any suggestions?

initial begin

    clk = 0;
    rst = 0;
    rst = 1;
    #1 rst = 0;
    wr_en = 0;
    rd_en = 0;

    for (i=0; i<1024; i=i+1) begin : wr_loop
        #1 wr_en = 1;
        din <= i;//$urandom_range(5,14);
        #1 wr_en = 0;
    end

    for (j=0; j<1024; j=j+1) begin : rd_loop
            #1 rd_en = 1'b1;
            #1 rd_en = 1'b0;
    end

    #900000 $finish;
end

    always #1 clk = ~clk;

simulation image link: (the full flag should raise after 1024 entries)

din <= 1 guarantees that the data is fassigned after your wr_en is set. Why do you use the non-blocking assighment there? You just create races in your test bench. Can you elaborate on 2. The read won't start from first pointer, instead starts with 4th read pointer.? — Serge

FriendFX FriendFX · Accepted Answer · 2017-09-22T06:14:41

I think you have a timing issue. If this is a FIFO synchronous to the rising clk edge, it may not correctly latch your wr_en or rd_en pulses.

For starters, I would try to keep wr_en simply high for the number of clk cycles you want to execute writes. Also, to avoid race conditions between your initial and always blocks, make clk generation part of the initial block and make sure the wr_en and rd_en signals change on the inactive (usually falling) edge of clk.

simulation errors in implementing xilinx fifo core

1 Answers