xilinx ise CHIPSCOPE PRO

Question

We are designing an 8 bit adder in verilog. Code is

module addsub (
    input     [7:0] dataa,
    input     [7:0] datab,
    input           clk,
    output reg[8:0] result
  );

  always@(posedge clk)
  begin
    result <= dataa + datab;
  end
endmodule

Can you give us simple steps to generate cores so that we run this code on SPARTAN 3E board using CHIPSCOPE PRO. We tried to using various forums and videos but could not find the exact steps.

Edit 1 - List of warnings:

Here are warning messages but no error messages.
The warnings are as follows:

WARNING:Xst:2211 - "ipcore_dir/aj_icon_core.v" line 16: Instantiating black box module <aj_icon_core>.
WARNING:Xst:2211 - "ipcore_dir/aj_vio_core.v" line 25: Instantiating black box module <aj_vio_core>.
WARNING:Xst:2211 - "ipcore_dir/aj_ila_core.v" line 36: Instantiating black box module <aj_ila_core>.
WARNING:Xst:1780 - Signal <CONTROL> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <CLK> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL1<13> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:Route:455 - CLK Net:CONTROL1<13> may have excessive skew because 
WARNING:Route:455 - CLK Net:result_3 may have excessive skew because
WARNING:Route:455 - CLK Net:result_6 may have excessive skew because
WARNING:Route:455 - CLK Net:result_4 may have excessive skew because
WARNING:Route:455 - CLK Net:result_7 may have excessive skew because
WARNING:Route:455 - CLK Net:result_8 may have excessive skew because
WARNING:Route:455 - CLK Net:result_1 may have excessive skew because
WARNING:Route:455 - CLK Net:result_0 may have excessive skew because
WARNING:Route:455 - CLK Net:result_5 may have excessive skew because
WARNING:Route:455 - CLK Net:result_2 may have excessive skew because
WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL1<13> is sourced by a combinatorial pin. This is not good design practic

Our code is as follows:

`timescale 1ns / 1ps
module addsub (
    inout [7:0] dataa,
    inout [7:0] datab,
    input clk1,
    output reg[8:0]result
  );

  /////////////////ICON////////////////////////////
  wire[35:0] CONTROL0;
  wire[35:0] CONTROL1;

  aj_icon_core YourInstanceName (
    .CONTROL0(CONTROL0),     // INOUT BUS [35:0]
    .CONTROL1(CONTROL1)      // INOUT BUS [35:0]
  );

  //////////////////////VIO//////////////////////////////////////
  wire[35:0] CONTROL;
  wire CLK;
  wire [8:0] SYNC_IN;
  wire [15:0] SYNC_OUT;

  aj_vio_core vio_core1 (
    .CONTROL(CONTROL0), // INOUT BUS [35:0]
    .CLK(clk1),          // IN
    .SYNC_IN(SYNC_IN),   // IN BUS [8:0]
    .SYNC_OUT(SYNC_OUT)  // OUT BUS [15:0]
  );

  //////////////////////////////////ila///////////////////////
  wire [31 : 0] TRIG0;
  aj_ila_core ila_core1(
    .CONTROL(CONTROL1), // INOUT BUS [35:0]
    .CLK(clk1),         // IN
    .TRIG0(TRIG0)       // IN BUS [31:0]
  );

  assign TRIG0={16'h0000, dataa ,datab}; //
  assign dataa= SYNC_OUT[15:8], datab= SYNC_OUT[7:0], SYNC_IN=result;

  always@(posedge clk1)
  begin
    result <= dataa + datab;
  end
endmodule

Answer 1

Create a new source (file) in your project: ChipScope Definition and Connection file (*.cdc) and follow the wizard's instructions.

Read UG750 for a step by step guide.

Edit1 - Example:

Sorry, currently I can only provide a VHDL example.

entity myExample is
  port (
    A : out : STD_LOGIC_VECTOR(31 downto 0);
    B : out : STD_LOGIC_VECTOR(31 downto 0);
    C : in  : STD_LOGIC_VECTOR(31 downto 0)
  );
end entity;

architecture rtl of myExample is
  subtype  T_XIL_CHIPSCOPE_CONTROL        is STD_LOGIC_VECTOR(35 downto 0);
  type     T_XIL_CHIPSCOPE_CONTROL_VECTOR is array (NATURAL range <>) of T_XIL_CHIPSCOPE_CONTROL;

  signal ControlBus : T_XIL_CHIPSCOPE_CONTROL_VECTOR(0 downto 0);

  signal ControlVIO_In   : STD_LOGIC_VECTOR(31 downto 0);
  signal ControlVIO_Out  : STD_LOGIC_VECTOR(63 downto 0);
begin
  -- instantiate a ICON IPCore with one ports
  ICON : entity PoC.xil_ChipScopeICON_1
    port map (
      control0 => ControlBus(0)
    );

  ControlVIO : entity myDesign.CSP_ControlVIO
    port map (
      CONTROL  => ControlBus(0),
      CLK      => SoFPGA_Clock,
      SYNC_IN  => ControlVIO_In,
      SYNC_OUT => ControlVIO_Out
    );

  A             <= ControlVIO_Out(31 downto 0);
  B             <= ControlVIO_Out(63 downto 32);
  ControlVIO_In <= C;
end;

This example uses an ICON IPCore with one control port. All signals are aggregated in a T_XIL_CHIPSCOPE_CONTROL type. (See xil.pkg.vhdl).

The pre-configured ICON cores can be downloaded from here. There are 15 ICON cores for each possible port count. In addition to that, there is a generic ICON wrapper xil_ChipScopeICON.vhdl to hide all cores and select the appropriate core by a generic.

The synchronous ports of ControlVIO are connected to A,B,C each of 32 bits which can be used by your adder.

Edit 2 - including netlists:

There are 3 ways on how to include netlists:

1)
Add the generated xco file to your project. It includes everything.

2)
Add the generated ngc file to your project. That's the netlist. The associated netlist constraint file (ncf) is loaded automatically.

3) (this works with VHDL; not tested with Verilog)
Add the generated wrapper vhdl file to your project and assign it to a library. Now specify one or more IPCore read directorys:

XST process properties -> Synthesis options page:
-read_cores - Read Cores
-sd - Cores Search Directories = d:\git\....\IPCores

(clickable)

This image shows my ChipScope ICON wrapper for 1..15 ports in the background. 15 VHDL files are loaded as placeholders. In the Forground, you can see the XST properties and the configured search path. Use '|' to separate multiple directories.

XST should report found netlists in the XST report (syr file) if Read Cores is enabled.