Xilinx ISE - Maximum frequency

0
votes

I'm trying to synthetize any simple project in ISE for Spartan 6. When I use Clocking Wizard for clk generator with f = 40 MHz (100Mhz external oscillator), XST says:

Timing Summary:

Speed Grade: -3

Minimum period: 9.482ns (Maximum Frequency: 105.458MHz) Minimum input arrival time before clock: 2.623ns Maximum output required time after clock: 3.597ns Maximum combinational path delay: 5.194ns

OK, but when I change clk frequency in core generator to 100MHz, the response is Maximum Frequency is about 47MHz ...

What is wrong? What is the right way to determine max frequency?

1
maxfrequencyxilinxspartan
Some questions: Have you applied timing constraints in synthesis? Have you checked if CoreGen changes the period generics of the mmcm accordingly? – Paebbels

1 Answers

1
votes

The reported maximum frequency in synthesis is only a rough estimation based on fanout, LUT levels, i/o-buffers, ...

The real timing analysis is done after Place & Route.

I have a project which already utilizes synthesis timing constraints (additional xcf-file), were XST reports f_max = 82 MHz. After P&R the design achieves 152 MHz :)