Xilinx ISE - Wrong maximum frequency?

Question

I have designed a simple Ripple Carry Adder in ISE and, after having synthesized it for my FPGA, the report says that the "maximum combinational path delay" is about 15 ns.

Then, I designed a Robertson multiplier (a sequential circuit), which contains an instance of my RCA. The report says that the "maximum combinational path delay" is about 7.5 ns and that the maximum frequency is about 130 MHz.

My question is: are these numbers right? Does the tool make some sort of "magic" optimization in order to "speed up" the adder inside the multiplier? Or is it just a wrong estimate?

I also found out that if I select "Keep Hierarchy" to "Yes", in the Synthesis Options, the frequency in the report becomes more or less consistent with the RCA's delay.

[EDIT] I'm posting the Synthesis text report and the Implementation (after Map) text report:

• RCA Synthesis text report: http://pastebin.com/1vqjNMA8
• RCA Map text report: http://pastebin.com/B9QxTpcz
• Robertson Multiplier Synthesis text report: http://pastebin.com/pUpnXPs6
• Robertson Multiplier Map text report: http://pastebin.com/yw93AEb0

Answer 1

If you've constructed your adder as an explicit combinational circuit, it's possible that MAP isn't recognizing it as an adder, and thus isn't able to use the carry chain circuitry present in the FPGA to implement it. This is likely to result in a much less performant design.

Implementing your adder using an HDL addition operator (e.g, assign c = a + b; in Verilog) will probably lead to a more optimal implementation. It'll also make your code much simpler.

Answer 2

Both of these numbers are useful, however the number reported during implementation tells you the fastest clock the design can reliably be used at on the FPGA you are generating hardware for. The synthesis number is more of an estimate of what the implementation number will be.

In synthesis your design is converted to hardware blocks, optimizations are done to simplify the logic into the simplest blocks. These blocks have timing parameters based on the FPGA family you are generating hardware for. These alone are used for the synthesis "maximum combinational path delay" estimate.

In implementation those blocks are mapped and routed onto the FPGA fabric, during which optimizations are done that can combine blocks potentially reducing the "maximum combinational path delay". Note that the delay can also increase when additional routing is needed for large or complex designs. At this point since the design has been mapped and routed onto physical hardware, worst case delays can be calculated on the mapped and routed design.

One thing that could have happened, is that your multiply accumulate got mapped onto a "hard" DSP block which contains a multiplier with pre and post adder logic. In this case it would have better timing since the DSP blocks have higher execution frequencies than LUT mapped adder/multiplies. The reason that synthesis would not show the timing is because there are relatively few DSP blocks and it makes a safe assumption in case there aren't enough DSP blocks to go around.