Maximum path delay in a simple combinational circuit

Question

I want to calculate the maximum path delay for a combinational circuit in Xilinx ISE. I'm familiar with the sequential circuits and I know how to work with timing constraints and the timing reports generated after P&R. But with no clock in the design, I do not know what should I do? Is it necessary to add clock in every combinational design so that it can be figured that how much the maximum path delay is? For example, for the following VHDL code of a full adder, how can I measure the maximum path delay?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity full_adder_vhdl_code is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end full_adder_vhdl_code;

architecture gate_level of full_adder_vhdl_code is

begin

S <= A XOR B XOR Cin ;
Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;

end gate_level;

This is not a VHDL question, but a Xilinx ISE question. You should read the Xilinx user guide on timing analysis. It's on the website. P.s. you should switch to Vivado. — JHBonarius

vipin vipin · Accepted Answer · 2017-11-04T13:37:41

This can be easily done in Xilinx ISE. You don't have to add any clock.

Just synthesis the code as it is. And then watch the console tab. The synthesis status will be displayed there. The delay you require is shown at the end of this report.

When I synthesised your code in ISE 14.6, I got this:

Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 0.776ns

========================================================================

Process "Synthesize - XST" completed successfully

Maximum path delay in a simple combinational circuit

1 Answers