Im trying to simulate a Xilinx GTXE2 transceiver with GHDL. In GTXE2_CHANNEL.vhd I got an error that 'std_logic_arith' can't be found in library 'ieee'.
First off all, here is my machine setup:
- Windows 7 (pro, x64, german)
- PowerShell 4.0
- Python 3.4
- Xilinx ISE 14.7 (x64, english)
- Xilinx Vivado 2014.2 (x64, english)
- GHDL 0.31 for Windows (http://sourceforge.net/projects/ghdl-updates/)
So question 1: Is this package included in GHDL?
I tried to change the VHDL standard to VHDL-2008 --std=08
, but this option is not recognized by ghdl, so I'm currently compiling with VHDL-2002. But nothing changed.
I also tried to include the IEEE sources manually from Xilinx' vhdl source folder C:\Xilinx\14.7\ISE_DS \ISE\vhdl\src\ieee
. But when I compile std_logic_arith it complains about a missing std_logic_1164, which is normally found. In addition to this, there is is a issue with the FOREIGN attribute in std_logic_1164.
So this is my file list/compile order to compile (a modified version of Xilinx' *.prj-files):
# board and device configuration
#vhdl poc "tb/common/my_config_KC705.vhdl"
# IEEE packages
#xilinx ieee "ieee/std_logic_1164.vhd"
#xilinx ieee "ieee/std_logic_arith.vhd"
# Xilinx Packages and Primitives
xilinx unisim "unisims/unisim_VCOMP.vhd"
xilinx unisim "unisims/unisim_VPKG.vhd"
xilinx work "unisims/primitive/FD.vhd"
xilinx work "unisims/primitive/BUFG.vhd"
xilinx work "unisims/primitive/BUFR.vhd"
xilinx work "unisims/secureip/GTXE2_CHANNEL.vhd"
This list gets translated into GHDL commands, which were executed in a temp directory:
C:\Program Files (x86)\GHDL\0.31\bin\ghdl.exe -a --std=02 -P. --work=poc "D:\VHDL\git\SATAController\lib\PoC\tb\common\my_config_KC705.vhdl"
GHDL Messages:
D:\VHDL\git\SATAController\lib\PoC\tb\common\my_config_KC705.vhdl:52:14:warning: package "my_config" does not require a body
C:\Program Files (x86)\GHDL\0.31\bin\ghdl.exe -a --std=02 -P. --work=unisim "C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\unisims\unisim_VCOMP.vhd"
C:\Program Files (x86)\GHDL\0.31\bin\ghdl.exe -a --std=02 -P. --work=unisim "C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\unisims\unisim_VPKG.vhd"
C:\Program Files (x86)\GHDL\0.31\bin\ghdl.exe -a --std=02 -P. --work=work "C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\unisims\primitive\FD.vhd"
C:\Program Files (x86)\GHDL\0.31\bin\ghdl.exe -a --std=02 -P. --work=work "C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\unisims\primitive\BUFG.vhd"
C:\Program Files (x86)\GHDL\0.31\bin\ghdl.exe -a --std=02 -P. --work=work "C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\unisims\primitive\BUFR.vhd"
C:\Program Files (x86)\GHDL\0.31\bin\ghdl.exe -a --std=02 -P. --work=work "C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\unisims\secureip\GTXE2_CHANNEL.vhd"
GHDL Messages:
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\unisims\secureip\GTXE2_CHANNEL.vhd:34:10: primary unit "std_logic_arith" not found in library "ieee"
And finally the FOREIGN attribute errors in ieee.std_logic_1164:
PS D:\VHDL\git\SATAController\lib\PoC\temp\ghdl> & 'C:\Program Files (x86)\GHDL\0.31\bin\ghdl.exe' -a --std=02 '-P.' --work=ieee 'C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd'
GHDL Messages:
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:211:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:212:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:213:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:214:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:215:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:216:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:218:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:219:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:220:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:221:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:223:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:224:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:225:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:227:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:228:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:229:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:231:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:232:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:233:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:235:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:236:15: value of 'FOREIGN attribute does not begin with VHPIDIRECT
C:\Xilinx\14.7\ISE_DS\ISE\vhdl\src\ieee\std_logic_arith.vhd:238:15: 'FOREIGN allowed only for architectures and subprograms
Question 2: How can I compile ieee.std_logic_1164?
Everyone with an installed GHDL environment can test this example. The my_config_KC705.vhdl is not needed by the Xilinx libraries.
What is the purpose of this?
- iSim simulation is very slow -> circa 15 ns sim-time is computed in 1 second cpu-time; 100 us -> 40 minutes of waiting
- iSim uses circa 2.6 GiB of main memory - may be GHDL is thriftier
- xSim has some complains about our VHDL library - so iSim is currently option #1
- I previously tested GHDL with Xilinx primitives and it worked, so the next challenge is to simulate a secureip component :)
- if I find enough time, I'll also try QuestaSim