Implement VHDL/Verilog only using lookup tables in Xilinx ISE

Question

Is there any way of telling ISE to synthesize my VHDL/Verilog code into combinational circuits consisting only of look-up tables? I would like to avoid multiplexers, multipliers, and the like in the tech schematic... and wouldn't mind having an unoptimized (with many components than is optimal) version because of this preference.

Thanks SOCommunity!

Answer 1

There is a way to do that. Look at the XST user guide for switches that control the use of the primitives you want to avoid:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/xst_v6s6.pdf

or:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/xst.pdf

depending on your target architecture.

For example, to avoid DSP blocks use:

-use_dsp48 no

To avoid automatic packing into BRAMs use:

-auto_bram_packing no

This switch can also be useful:

-slice_utilization_ratio

as will others.

I have a convenient way to look at the available switches, along with some explanation of what they do, on my site:

https://www.boldport.com/flow/#new/options

(click 'Edit', and then 'More options...')

I hope this helps.

Answer 2

In Xilinx you can use the Language templates for this purpose. Select the device you are using and check the available type of LUT's and other components. You can individually instantiate these LUT in your design.

You may have to switch off the "optimization during synthesis" option in XST properties to make this work correctly.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/ise_p_lt_using_language_templates.htm