Xilinx VHDL Multicycle constraints

Question

I have some code that's running on a Xilinx Spartan 6, and it currently meets timing. However, I'd like to change it so that I use fewer registers.

signal response_ipv4_checksum     : std_logic_vector(15 downto 0);
signal response_ipv4_checksum_1   : std_logic_vector(15 downto 0);
signal response_ipv4_checksum_2   : std_logic_vector(15 downto 0);
signal response_ipv4_checksum_3   : std_logic_vector(15 downto 0);
…

process (clk)
begin
    if rising_edge(clk) then
        response_ipv4_checksum_3 <= utility.ones_complement_sum(x"4622",                  config.source_ip(31 downto 16));
        response_ipv4_checksum_2 <= utility.ones_complement_sum(response_ipv4_checksum_3, config.source_ip(15 downto 8));
        response_ipv4_checksum_1 <= utility.ones_complement_sum(response_ipv4_checksum_2, response_group(31 downto 16));
        response_ipv4_checksum   <= utility.ones_complement_sum(response_ipv4_checksum_1, response_group(15 downto 0));
    end if;
end process;

Currently, to meet timing, I need to split up the additions over multiple cycles. However, I have 20 cycles to actually compute this value, during which time the config value can't change.

Is there some attribute I can use (preferred) or line in the constraints (ucf) file that I can use so that I could simply write the same thing, but use no registers?

Just for a bit of extra code, in my UCF, I already have a timespec that looks like this:

NET pin_phy_rxclk TNM_NET = "PIN_PHY_RXCLK";
TIMESPEC "TS_PIN_PHY_RXCLK" = PERIOD "PIN_PHY_RXCLK" 8ns HIGH 50%;

Have you read about multicycle path constraints in the Xilinx Constraints Guide (cgd.pdf)? — user_1818839
I have. In the 12.1 Version, I wasn't able to see how I could convert their example to apply to code like this, and it appears that the multicycle section has been removed from the 14.2 version of cgd.pdf — Bill Lynch
Why do you need to reduce the number of registers - are you running out of them? (I usually run out of LUTs first!) — Martin Thompson
@MartinThompson: This is more for my personal knowledge. I haven't run out of resources yet. I also wonder if doing things like this would enable the map and par stage to finish quicker (since it would have more freedom to place the adders). — Bill Lynch

Martin Thompson Martin Thompson · Accepted Answer · 2013-02-05T14:09:58

I think you need a FROM:TO constraint:

TIMESPEC TSname=FROM “group1” TO “group2” value;

where value can be based on another timespec, like TS_CLK*4

So you'd adjust your process to only have flipflops on the output signals, create a timegroup with the inputs in it, another with the outputs in it, and use those for group1 and group2 .

So, group 1 would contain all the input nets /path/to/your/instance/config.source_ip and /path/to/your/instance/response_group. It might be easier to create a vector input to the entity and wire up the config/response_group signals outside of it. Then you can just use /path/to/your/instance/name_of_input_signals.

Group 2 would contain /path/to/your/instance/response_ipv4_checksum.

And, as you comment, you can use TS_PIN_PHY_RXCLK*4 (assuming it is a time, not a frequency - otherwise you have to do a /4 I think)

Xilinx VHDL Multicycle constraints

1 Answers