Conditional UCF statements or conditional UCF file inclusion

Question

Is there a way/workaround to use statements in a UCF file conditionally, or, can UCF files be included into other UCF files conditionally?

The problem I'm facing is that I have a top module with a set of generics which conditionally instantiate or remove certain submodules from the top module via generate statements.
However, most of these submodules have timing constraints defined in the projects UCF file. Somewhere during map or par the build process is aborted stating that an instance the UCF file is refering to does not exist (which is correct since the instance was never created due to the choice of generics in the top module).

Whats the best possible way to achieve some sort of "conditional constraint", which can avoid this problem? (beside the obvious preprocessor/script which fingers around in my UCF file)

PS: I'm using the Xilinx ISE 14.4 / Vivado 2012.4 command line tools.

Answer 1

This question has been asked several times:

http://forums.xilinx.com/t5/Design-Entry/include-and-ifdef-for-ucf-files/td-p/77822

http://forums.xilinx.com/t5/Design-Entry/Conditional-inclusion-of-ucf-files/td-p/195684

Short answer is no, not possible unfortunately.

Your best bet is to create 2 separate UCF files and either create a script to point to one or the other or to manually replace it each time you turn on/off your generic switch.

Answer 2

IF you are using Vivado, then you should know that UCF files are no longer supported under the Vivado synthesis. Unless you have to use XST, then you no longer limited to use the out dated UCF file format for your constraints. Vivado is using XDC constraints, which are a sub set ot TCL, which means you can write a code with conditions to handle your constraints in any way you desire.

You can take a look at the UG 903 from Xilinx for moredetails on how to use the constraints in the latest version of their tools:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug903-vivado-using-constraints.pdf

Answer 3

Another potential solution would be to use Xilinx synthesis attributes.

This can be done to constrain timing of nets, just like the UCF can.

The difference is, attributes can be done inline in VHDL, near the signal declaration. It's clunky, though.

The right solution likely depends on how many constraints you have.

Answer 4

I upvoted FarhadA's answer, but I wanted to emphasize the point that XDC files are TCL scripts and so they can include conditionals and for loops. So much better than UCF files.

Another advantage of the constraint processing in Vivado is that if it encounters a constraint that does not match the design, it issues a Critical Warning and continues.