Top module VHDL with no inputs and outputs

Question

I have two files, master.vhd and slave.vhd, both synthetize without errors or warnings. I want to create a structural top module and connect them. I'm using Xilinx ISE 14.2.

My top.vhd file looks like this:

library ieee;
use ieee.std_logic_1164.all;

entity top is
end top;

architecture structural of top is

signal reset, clk : std_logic;
signal req, ack, sig : std_logic;

begin

    master : entity work.master_v10_zad1(rtl)
    port map(
        reset => reset,
        clk => clk,
        req => req,
        ack => ack,
        sig => sig
    );

    slave : entity work.slave_v10_zad1(rtl)
    port map(
        reset => reset,
        clk => clk,
        req => req,
        ack => ack,
        sig => sig
    );

end structural;

When I do it like this I can't synthesize it and get a lot of warnings like: WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected... blah blah

But if I add some uneeded ports in the top entity then it synthesizes ok, but I don't need the extra ports, they are just clutter!

My question is how do I connect the two modules with a top structural file (or any other way that works) and keep the design synthetisable?

user_1818839 user_1818839 · Accepted Answer · 2013-05-11T21:20:02

If it has no outputs then it cannot cannot produce any result or influence the world in any way, therefore it can safely be optimised away. This is a philosophical rather than a technical point, but, without outputs, what can it actually DO?.

That aside, you could provide sufficient outputs from the block to preserve its internals from optimisation, but simply not bring them out to external FPGA pins. There is a "disable IOB insertion" synthesis option which allows this. The normal use is for creating HDL IP which will later be integrated into another top level design, but it may serve your purpose as far as I understand it.

Top module VHDL with no inputs and outputs

1 Answers