Vhdl Up down counter using adder subtractor U in simulation

Question

I am trying to make a four bit up down counter using a 4 bit adder subtractor using structural modeling The problem is the input (A) of the adder subtractor needs to be updated to be equal the sum ,i tried making signals inside the process to fix this but it gives U in simulation also i cant set a to be equal output , but i had to write that the output is equal to A

Also ,the warning that signal s is to be 0 , i need it ti change 0 and 1 ,as its responsible for the up down counting , but it gives error when i try to set values for it in the test bench

I am not able to figure this out, any help is much appreciated

Simulation Errors : ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers. ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers. ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers. ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drive

Simulation Warnings : nput is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0.

This is the counter code 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity upDown is
    Port ( a: in STD_LOGIC_VECTOR(3 downto 0 );
             b : in STD_LOGIC_VECTOR(3 downto 0 );
            clk,reset,enable : in  STD_LOGIC  ;
           o : out STD_LOGIC_VECTOR(3 downto 0 )
            );
end upDown;

architecture Behavioral of upDown is

component addersub4bits is 
 Port ( a,b : in  STD_LOGIC_VECTOR (3 downto 0);
        y : out  STD_LOGIC_VECTOR (3 downto 0);
        s : in  STD_LOGIC  );
 end component ;

 signal s : STD_LOGIC ;
-- signal tmp2 : STD_LOGIC_VECTOR(3 downto 0) ;
signal outputsignal: STD_LOGIC_VECTOR(3 downto 0) ; --inside process

begin

ad : addersub4bits  port map( a,"0001" ,outputsignal ,s) ;

process (clk,reset,enable) 

begin

if(reset= '1' ) 
then outputsignal <= "0000"; 

elsif(clk' event and clk='1' ) then 
if(enable ='1' ) then 
outputsignal<=a ;

else

outputsignal<=outputsignal ;   --zay mahowa 
end if ;
end if ;
end process ;
--o <= tmp ;
o <=outputsignal ;

end Behavioral ;

THe adder subtractor

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity addersub4bits is
Port ( a,b : in  STD_LOGIC_VECTOR (3 downto 0);
y : out  STD_LOGIC_VECTOR (3 downto 0);
s : in  STD_LOGIC);

end addersub4bits;

architecture dataflow of addersub4bits is


begin

 Process(a,b,s) 
 begin
if (s='1') then 

y<= (a + b) ;

else
y<=(a-b) ;

end if ; 

end process ;


end dataflow;

TESTBENCH

-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY uD_testbench IS
END uD_testbench;

ARCHITECTURE behavior OF uD_testbench IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT upDown
    PORT(
         a : IN  std_logic_vector(3 downto 0);
         b : IN  std_logic_vector(3 downto 0);
         clk : IN  std_logic;
         reset : IN  std_logic;
         enable : IN  std_logic;
         o : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal a : std_logic_vector(3 downto 0) := (others => '0');
   signal b : std_logic_vector(3 downto 0) := (others => '0');
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal enable : std_logic := '0';

    --Outputs
   signal o : std_logic_vector(3 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: upDown PORT MAP (
          a => a,
          b => b,
          clk => clk,
          reset => reset,
          enable => enable,
          o => o
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for 100 ns ;
        clk <= '1';
        wait for 100 ns ;
   end process;


   -- Stimulus process
   stim_proc: process
   begin        
      reset <= '1' ;enable <= '0' ; wait for 150 ns ;
        reset <= '0'; wait for 300 ns ;

        --enable <= '0' ; wait for 200 ns ;
        enable <='1' ;wait ;
   end process;

END;

deepsubmicron deepsubmicron · Accepted Answer · 2013-04-07T09:57:41

The output of the adder drives the signal outputsignal but your register also drives the same signal. Changing one of them should help. For example change the adder output to feed the register input and the register output to feed the adder input.

ad : addersub4bits port map( a=>outputsignal,b=>"0001" , y=>a ,s=>s) ;

You can now choose if you use the register output outputsignal (good coding style) or the adder output a as output of upDown.

Optional Tip1: When using the unresolved type std_ulogic instead of std_logic then a vhdl compiler must complain about a unresolved signal driven by multiple sources. So it is possible to find this kind of problems faster, even before the simulation starts. The disadvantage is that there is no IEEE.STD_ U LOGIC_UNSIGNED package in the VHDL standard.

Optional Tip2: The package ieee.numeric_std should be preferred instead of ieee.std_logic_arith which has some known problems.

Putting both tips together an add/sub can still be written like this:

if s='1' then 
  y<= std_ulogic_vector( unsigned(a) + unsigned(b));
else
  y<= std_ulogic_vector( unsigned(a) - unsigned(b));
end if;

Vhdl Up down counter using adder subtractor U in simulation

THe adder subtractor

1 Answers