VHDL error, even though I generate a bit file

Question

I have made this program in VHDL, alle syntax's are fine, and I have tried to double check all the port maps, but I get some warnings that causes the program not to work, even tough it can generate the bit file.. anybody here who can help please??

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;


    entity topMain is
    port(   clk   : in std_logic; 
          alarm : in std_logic_vector (1 downto 0);
        d_open : in std_logic_vector (1 downto 0);      
        d_closed  : in std_logic_vector(1 downto 0);        
        d_out : out std_logic_vector (1 downto 0));         
    end topMain;

    architecture Behavioral of topMain is

    type state_type is (S0,S1,S3);


    signal NS, Current_State : state_type;
    begin

    process (clk, alarm)
    begin

    if alarm ="11" then 
        Current_State <= S3;  -- 
    
    elsif rising_edge (clk) then 
        Current_State <= NS;   -- state change
    end if;
    end process;

    --------------------------------


    process(Current_State,d_open, d_closed, clk)
    begin
        case Current_State is
  
    ----
    when S3 =>      d_out <= "11";
            if (d_open = "10") then
                        NS <= S3;

                    elsif (d_closed = "01") then
                    NS <= S3;
                    elsif (d_closed = "00") then 
                    NS <= S3;

            end if;
        
----
              
      when S0 =>         d_out <= "10"; -- open door
                     if ( d_open = "10" ) then
                      NS <= S0;
                             
                             elsif (d_closed= "01") then
                             NS <= S1;
                             elsif (d_closed = "10") then
                             NS <= S0;
                        
                else   
                    NS <= S0;
                end if;

                     
    when S1 =>        d_out <= "01";  -- open door
                if ( d_closed = "01" ) then
                    NS <= S1;
                    elsif (d_open <= "10") then
                    NS <= S0;
                    elsif (d_open <= "01") then
                    NS <= S1;
                else   
                    NS <= S1;
                end if;
            
        end case;
   
   end process;
    end Behavioral;

And in case anybody can take a look at it, this is the full project. Its a simple program containg a finite state machine with 3 changes, simulating a burglar alarm. When alarm is off, you can open door and close it, but if its on, you cant do anything. at lease thats what i was trying to make, altough i am newbie. Please forgive me for any inconvenience it may cause you.

http://www.abmy.dk/BAlarm.zip

The warnings I am getting right now:

WARNING:Xst:819 - "C:/Xilinx/OP/BAlarm/topMain.vhd" line 36: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: WARNING:Xst:737 - Found 3-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:PhysDesignRules:372 - Gated clock. Clock net top/NS_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:Route:455 - CLK Net:top/NS_not0001 may have excessive skew because

What exactly are the warnings you are getting? What exactly do you mean when you say it "doesn't work"? Have you tried running a simulation? You must help us if you want us to help you. — user1619508
I have added all the warninngs i am getting so far in the question.. — abmy

Morten Zilmer Morten Zilmer · Accepted Answer · 2013-12-06T07:15:02

The NS signal is not assigned in all branches of the combinatorial process process(Current_State, d_open, d_closed, clk), which will infer latches; see also https://stackoverflow.com/a/20394822/2352082 and https://stackoverflow.com/a/20411227/2352082

The code:

when S3 => d_out <= "11";
           if (d_open = "10") then
             ns <= S3;
           elsif (d_closed = "01") then
             ns <= S3;
           elsif (d_closed = "00") then
             ns <= S3;
           end if;

does not have an else, so if neither of the previous conditions are TRUE, then NS is not assigned, which results in a latch inferred by synthesis.

You may fix this by adding an else with proper assign NS value assign, like:

           ...
           else
             ns <= S0;  -- TBD[S0 is only example; use correct value]
           end if;

I don't see any signals missing in the process sensitivity list, but clk is included and not required in the last one, since this process implements combinatorial design.

VHDL error, even though I generate a bit file

1 Answers