So I'm trying to implement a I2C master on a FPGA, and I get the following Errors. Does someone know how to solve them? Thanks!
WARNING:Xst:646 - Signal <thirdaddress> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <secondaddress> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <firstaddress> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_sda> created at line 44. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_sda> created at line 44. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 3-bit latch for signal <sendcount>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:1293 - FF/Latch <XLXI_9/sendcount_2> has a constant value of 0 in block <top_level>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <XLXI_9/sendcount_1> has a constant value of 0 in block <top_level>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <XLXI_9/sendcount_0> has a constant value of 0 in block <top_level>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <XLXI_9/current_state_FSM_FFd1> has a constant value of 0 in block <top_level>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1294 - Latch <XLXI_9/Mtridata_sda> is equivalent to a wire in block <top_level>.
WARNING:Xst:1294 - Latch <XLXI_9/Mtrien_sda> is equivalent to a wire in block <top_level>.
Here is the code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity i2cmaster is
Port ( sda : inout STD_LOGIC;
scl : out STD_LOGIC;
sclclk : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
dataout : out STD_LOGIC_VECTOR (7 downto 0);
resettodivider : out STD_LOGIC);
end i2cmaster;
architecture Behavioral of i2cmaster is
type state_type is (startstate1, startstate2, sendaddress1, acknowlegde1, sendinternaladdress, acknowlegde2, startstate3, startstate4, sendaddress2, acknowlegde3, readdata, notacknowlegde, stopstate );
signal current_state : state_type;
signal next_state : state_type :=startstate1;
signal firstaddress: std_logic_vector(7 downto 0);
signal secondaddress: std_logic_vector(7 downto 0);
signal thirdaddress: std_logic_vector(7 downto 0);
signal sendcount: integer range 0 to 7 := 0;
signal temp : std_logic := '0';
signal tempdata : std_logic_vector(7 downto 0):="00000000";
begin
firstaddress<="10101010"; -- Slaveaddress + Writebit
secondaddress<="10101010"; -- Internal Address(first)
thirdaddress<="10101010"; -- Slaveaddress + Readbit
process(current_state, sda, sclclk, temp, sendcount, firstaddress, secondaddress, thirdaddress)
begin
case current_state is
------------------------
when startstate1 =>
temp<='0';
sendcount <=0;
resettodivider <='1';
sda<='1';
next_state <= startstate2;
------------------------
when startstate2 =>
temp<='0';
sendcount <=0;
resettodivider <='0';
sda<='0';
if sclclk = '0' then
next_state <= sendaddress1;
else
next_state <= startstate2;
end if;
------------------------
when sendaddress1 =>
resettodivider <='0';
if sendcount <= 7 then
if sclclk = '0' and temp='0' then
sda<=firstaddress(sendcount);
sendcount <= sendcount + 1;
temp<='1';
next_state<=sendaddress1;
elsif sclclk='1' then
temp<='0';
sendcount <=sendcount;
next_state<=sendaddress1;
else
temp<='0';
sda<='Z';
sendcount <= sendcount;
next_state<=sendaddress1;
end if;
else
temp<='0';
sendcount <= 0;
next_state<=acknowlegde1;
end if;
------------------------
when acknowlegde1 =>
temp<='0';
resettodivider <='0';
sendcount <=0;
if sclclk='1' then
if sda ='1' then
next_state<=startstate1;
else
next_state<=acknowlegde1;
end if;
else
next_state<=sendinternaladdress;
end if;
------------------------
when sendinternaladdress =>
resettodivider <='0';
if sendcount <= 7 then
if sclclk = '0' and temp='0' then
sda<=secondaddress(sendcount);
sendcount<= sendcount + 1;
temp<='1';
next_state<=sendinternaladdress;
elsif sclclk='1' then
temp<='0';
sendcount <=sendcount;
next_state<=sendinternaladdress;
else
temp<='0';
sendcount <= sendcount;
next_state<=sendinternaladdress;
sda<='Z';
end if;
else
temp<='0';
sendcount<= 0;
next_state<=acknowlegde2;
end if;
------------------------
when acknowlegde2 =>
sendcount <=0;
temp<='0';
resettodivider <='0';
if sclclk='1' then
if sda ='1' then
next_state<=startstate1;
else
next_state<=acknowlegde2;
end if;
else
next_state<=startstate3;
end if;
------------------------
when startstate3 =>
sendcount <=0;
temp<='0';
resettodivider <='1';
sda<='1';
next_state <= startstate4;
------------------------
when startstate4 =>
temp<='0';
resettodivider <='0';
sda<='0';
sendcount <=0;
if sclclk = '0' then
next_state <= sendaddress2;
else
next_state <= startstate4;
end if;
------------------------
when sendaddress2 =>
resettodivider <='0';
if sendcount <= 7 then
if sclclk = '0' and temp='0' then
sda<=thirdaddress(sendcount);
sendcount<= sendcount + 1;
temp<='1';
next_state<=sendaddress2;
elsif sclclk='1' then
sendcount<= sendcount;
temp<='0';
next_state<=sendaddress2;
else
sendcount<= sendcount;
temp<='0';
sda<='Z';
next_state<=sendaddress2;
end if;
else
temp<='0';
sendcount <=0;
next_state<=acknowlegde3;
end if;
------------------------
when acknowlegde3 =>
temp<='0';
sendcount<=0;
resettodivider <='0';
if sclclk='1' then
if sda ='1' then
next_state<=startstate1;
else
next_state<=acknowlegde3;
end if;
else
next_state<=readdata;
end if;
------------------------
when readdata =>
resettodivider <='0';
if sendcount <= 7 then
if sclclk = '0' and temp='0' then
tempdata(sendcount)<=sda;
tempdata<=tempdata;
sendcount<= sendcount + 1;
temp<='1';
next_state<=readdata;
elsif sclclk='1' then
tempdata(sendcount)<='0';
temp<='0';
sendcount <= sendcount;
next_state<=readdata;
else
temp<='0';
tempdata(sendcount)<='0';
sendcount <= sendcount;
next_state<=readdata;
end if;
else
temp<='0';
tempdata(sendcount)<='0';
sendcount <= 0;
next_state<=notacknowlegde;
end if;
------------------------
when notacknowlegde =>
sendcount<=0;
temp<='0';
resettodivider <='0';
if sclclk='0' then
next_state<=stopstate;
sda<='Z';
else
sda<='1';
next_state<=notacknowlegde;
end if;
------------------------
when stopstate =>
sendcount<=0;
temp<='0';
sda<='0';
resettodivider <='1';
next_state<=startstate1;
------------------------
when others =>
sendcount<=0;
temp<='0';
resettodivider <='0';
next_state<=startstate1;
sda<='Z';
scl<='Z';
end case;
end process;
-------
process(clk, reset)
begin
if (reset='1') then
current_state <= startstate1;
elsif rising_edge(clk) then
current_state <= next_state;
end if;
end process;
-------
scl<=sclclk;
dataout<= tempdata;
end Behavioral;
