about Synplify VHDL (code imported from Xilinx ISE)

1
votes

I'm start to work with Synopsys Synplify. Import my Xilinx ISE project (fully work).

Try to run and receive - "No matching overload for to_integer" for this line

rgb(7 downto 0) <= color_lut(result_reg(to_integer(unsigned(x(2 downto 0))-1 )));

What can I do to adopt this piece for Synplify?

1
vhdlxilinx
Can you specify what libraries and packages you have referenced in your design? For example, library ieee; use ieee.std_logic_1164.all; etc... – Josh
Also specifying the version of Synplify could also be helpful. – Josh
Sure,library IEEE, ieee_proposed; ---- use IEEE.STD_LOGIC_1164.ALL; ---- use ieee.numeric_std.all; ---- use ieee_proposed.fixed_pkg.all; ---- – fpgaiua

1 Answers

0
votes

You should be able to use the following libraries in synplify:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.fixed_pkg.all;

Under implementation options > VHDL Tab make sure you enable "VHDL 2008" checkbox. I don't think it is enabled by default. This could be your problem.