Bi-directional communication using Asynchronous FIFO?

2
votes

I am trying to interface a module (let's call it main_module) with a Dual Port Block RAM memory generated by the Xilinx CORE Generator. Both the modules transmit and receive data with each other and run at markedly different clock speeds. In order to cater for the synchronization issues faced in interfacing, I have decided to use an asynchronous FIFO (also generated by the Xilinx CORE Generator). With regards to this I have some confusions:

  1. How can I efficiently change the assignment of FIFO Read and Write clocks for bi directional communication between the main_module and BRAM? In the memory write mode, the WR_CLK of FIFO would be that of the main_module and the RD_CLK of FIFO would be that of the BRAM module. In the memory read mode, the clocks would be oppositely assigned. Same will be with the DIN and DOUT pins assignment of FIFO. The read and write modes are selected through input signals.
  2. What about the memory addresses? They would be generated in the main_module and have to be passed to the BRAM. Should synchronization be done for that too? If yes then what would be the most efficient manner for that?

Input and Output Data with an AFIFO

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synchronizationxilinxfifobidirectional
Can you clarify what you are planning to do with the Bram. The Fifo should be enough for the communication and typically you don't need an additional Bram. Just use 2 Fifos for 2-way communication. Check out also xmp components from Xilinx. They are much more accessible than core generator cores for memory and fifos, and also have handy clock domain crossing stuff. - FritzDC
Another top level module will be accessing the BRAM contents ultimately. Basically my main_module running at clockA sends (or receives) data and address to be written to (or read from) the BRAM clocked at clockB. This poses synchronization and setup/hold time issues. I was planning to introduce a FIFO in between the BRAM and main_module. - Candy
It sounds a bit that you are trying to over engineer a common setup, where just a bram with two ports in different clock domains would suffice. Any other solution will be less efficient in both resource usage and maximum throughput. For any and all multi-bit signal clock domain crossing, best bet is to use fifos. One for each direction. BTW, you don't clock the bram, but the interface port. - FritzDC
Not exactly over engineer, as other modules will also have access to the BRAM at different times and only my main_module has a different clock speed! - Candy
Ok, I didn't picture in the top module, sorry. I'll make proper answer with this info. - FritzDC

1 Answers

1
votes

Three options come into mind in order of preference:

1) Switch to AXI in your BRam interface and use AXI components and protocol for multi-master memory access. It might seem like an overkill at first, but whatever you make from the scratch will need to work towards similar principles on ad-hoc basis, which typically is much more time consuming than using purpose built industry standards methods.

2) (Re)Architect the design so that one BRam port is not needed to be shared. For example duplicate the data so that there is always just one clock per port, i.e. write to two BRams is the data is needed by two parties.

3) As you propose, have a Fifo for the clock that is not used in the port natively. You will need to have both data and address in this Fifo. Writes are thus quite straining-forward, but for reads you'll need also Fifo (or XMP Clock Domain Crossing Synchronizer) for the return channel and some protocol to handle the read.