The diagram of my verilog firmware is like that:
In my diagram, I have 6 16-bit data and 6 valid_data are outputs from 6 same module being generated by generate function. The function of valid_data is to notify when 16-bit data is written into FiFo (Native and IP core) supplied by Xilinx. Because there are two clocks domain in my firmware, so I use synchronous FiFo as a handshaking between two clocks domain to ensure that 6 16-bit data are obtained correctly in clock domain 120 MHz.
After that I put 6 16-bit output data from 6 synchronous FiFo to one 96-bit variable. I would like to use the 6 valid signal from 6 synchronous Fifos to generate the new valid signal to notify to asynchrous FiFo that 96-bit data is ready to be written into the asynchronous FiFo. But I have one problem:
I think that the 6 16-bit data go to the FIFO at the same time so the output from Synchronize of Fifo need to appear at the same time. But when I use chipscope to check the valid signal, I do not understand why the valid signal going out FIFO is not same time at the figure and it makes me very difficult to generate the new valid signal. Someone can tell me the reason why this happened.
6 valid signal from 6 Fifos and new valid signal checked by Chipscope
_ valid check[85:81] are 6 valid signals from 6 FiFos.
_ check_ir_valid is variables to accumulate 6 valid signals
_ valid_to_fifo is the new valid signal.
Because 6 valid signal do not appear at the same time so I also thought another method to so also use the one 6-bit variable to accumulate 6 valid signal. When this variable collect enough 6 valid signal from FiFo, it means that 6-bit variable equal 6'h3F, I will have the new valid signal for asynchronous FiFo. Are there any potential risks with this method ?