Verilog: "Unspecified I/O standard" and "Poor placement for routing between an IO pin and BUFG" Errors

Question

I am fairly new to Verilog and FPGA development. I am currently working on a project to control two motors using a Basys 3 board and an H bridge.

The module is currently built to use PWM to control the motor speed, sending the output to the ena and enb pins on the H-Bridge. The H inputs are currently constant for the sake of testing the PWM control.

Well long story short I have run into a variety of I/O errors that I just haven't been able to fully wrap my head around.

Here is my primary module:

module RDrive(
    input clock,
    input BUTTON,
    input H1, H2, H3, H4,
    output ena, enb
    );

    wire clock, BUTTON, H1, H2, H3, H4;

    reg[1:0] speed;
    reg[3:0] counter, width;
    reg PWMtemp;

    wire ena, enb;

    // initial values
    initial begin
        counter <= 4'b0000;
        speed = 0;
        PWMtemp <= 0;
        width <= 0;
    end

    // Every button press increments speed value
    always @ (posedge BUTTON)
    begin
        speed <= speed + 1;
        // width adjusted for PWM module
        case (speed)
            2'b00 : width <= 4'b0000;
            2'b01 : width <= 4'b0101;
            2'b10 : width <= 4'b1010;
            2'b11 : width <= 4'b1111;
            default : width <= 4'b0000;
        endcase
    end

    // PWM
    always @ (posedge clock)
    begin
        if (counter < width) PWMtemp <= 1;
        else PWMtemp <= 0;
        counter <= counter + 1;
    end

    assign ena = PWMtemp;
    assign enb = PWMtemp;

endmodule

Here is my test bench:

module RDrive_TB(

    );
    reg clock;
    wire ena = 0;
    wire enb = 0;
    reg BUTTON, H1, H2, H3, H4;

    initial begin
        BUTTON = 0;
        clock = 0;
        // H values for testing PWM speed control
        H1 = 1;
        H2 = 0;
        H3 = 1;
        H4 = 0;

        // Simulating button presses
        #1000;
        BUTTON = 1;
        #10;
        BUTTON = 0;

        #1000;
        BUTTON = 1;
        #10;
        BUTTON = 0;

        #1000;
        BUTTON = 1;
        #10;
        BUTTON = 0;

        #1000;
        BUTTON = 1;
        #10;
        BUTTON = 0;

    end

    // clock generator
    always begin
        #1 clock = ~clock;
    end

    RDrive RDriveTest(clock, BUTTON, H1, H2, H3, H4, ena, enb);


endmodule

and here are my constraints:

set_property PACKAGE_PIN W5 [get_ports CLK100MH]
set_property IOSTANDARD LVCMOS33 [get_ports CLK100MH]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports 
CLK100MH]

set_property PACKAGE_PIN U18 [get_ports BUTTON]
set_property IOSTANDARD LVCMOS33 [get_ports BUTTON]

##Sch name = JA8
set_property PACKAGE_PIN K2 [get_ports {enb}]
set_property IOSTANDARD LVCMOS33 [get_ports {enb}]

The first error (occurred during implementation) that I got was this:

ERROR: [Place 30-574] Poor placement for routing between an IO pin and BUFG.

I did some research, and I think the problem was a result of always @ (posedge BUTTON) not being exactly in time with the clock. So I added this line to the constraints to ignore the error:

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets BUTTON_IBUF]

This allowed me to run the implementation successfully. However, I encountered the following error when attempting to generate the bitstream:

ERROR: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 4 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value.

From what I understand, this error occurs when inputs/outputs are not assigned an initial value, so they assume whatever the 'DEFAULT' value is. I fiddled around with the initial values and value types of each of the "problem pins" that were listed. I was able to fix most of them, but currently 'clock' is the only remaining problem pin. I've been trying to fix clock for a while now with no luck.

Some help would be greatly appreciated, thanks!

Oldfart Oldfart · Accepted Answer · 2018-10-09T06:38:20

1/ You should not use @ (posedge BUTTON) for two reasons:

You have not de-bounced the button so a single push can trigger multiple speed increments.
In simple design like that everything should run of a single clock.

You should synchronize your button input to the clock and then add a counter + logic to check if the signal is stable (bouncing has stopped).

2/ The error message is very clear and specific:

Unspecified I/O Standard: 1 out of 4 logical ports....

All I did was check all your I/O ports and check your pin constraints. I see no constraint for the ena signal.

Verilog: "Unspecified I/O standard" and "Poor placement for routing between an IO pin and BUFG" Errors

1 Answers