Automatic flag for compiler directive based on synthesis/simulation for xilinx/modelsim?

0
votes

I've got a large verilog project that I'm synthesizing onto a xilinx fpga and simulating in modelsim. There are a few modules wherein I'd like to simulate one version of said module and synthesize another. For example I have a parameterized reset debouncer, which counts a few milliseconds. Clearly for simulation this is annoying so before I simulate I change the debounce count to something like 10 clock cycles. Currently I have a flag (`define SIMULATION), which I comment out for synthesis. Then in my modules I utilize compiler directives like 'ifdef to compile a different version of the deouncer depending on synthesis/simulation:

 `ifdef SIMULATION
   button_debouncer #(1,5, 24)
`else
   button_debouncer #(1,12000000,24)
`endif
   resetdebounce(/**/
         // Outputs
         .debounced     (reset),
         // Inputs
         .clk           (clk),
         .button        (~reset_button));

While this works it requires that I comment in/out `define SIMULATION every time I switch from modlesim to ISE. I often forget, waste time, etc, etc.

Is there an automatic way to determine which tool is being used? Eg I could say something like ifdef XILINX orifdef MODELSIM instead of my `ifdef SIMULATION hack? Thanks a lot!

3
simulationverilogfpgaxilinxmodelsim
Both @CliffordVienna and dwikle solutions work well. Depending on your tool chains either or both solutions work great. – Doov

3 Answers

4
votes

According to the Xilinx ISIm User Guide (UG660, v14.3, page 44), isim predefines the macro XILINX_ISIM (to the value 1). So just use XILINX_ISIM instead of SIMULATION.

5
votes

Mentor Graphics simulators (ModelSim and Questa) will define the MODEL_TECH preprocessor macro.

So you can do:

`ifdef MODEL_TECH
  // code for simulation with modelsim
`else
  // code for synthesis
`endif
0
votes

Try passing +define+SIMULATION to vlog as a command-line argument.