Verilog module instantiation

Question

I am having a bit of trouble instantiating a module in verilog. I am using the Altera Quartus platform to develop and simulate the verilog code.

I have followed this example (among several others): http://www.asic-world.com/verilog/verilog_one_day4.html

I have written a module (maximum) which finds the maximum between two signed inputs.

Another module I am developing is a systolic array for genetic sequence alignment. The details are not important, however when I try to instantiate a maximum module I get an error.

This is my code so far:

module maximum (a, b, out);
input signed [15:0] a;
input signed [15:0] b;
output reg signed [15:0] out;
  always @* begin
    if (a>b)
      assign out = a;
    else
      assign out = b;
  end
endmodule

and I instantiate in another module systolic_PE (all of this is in the same file seqalign.v)

maximum m0(.a(tempB), .b(diag), .out(tempA));

And I get the error :

'Verilog HDL syntax error at seqalign.v(139) near text "m0"; expecting "<=" or "="'

I checked everything I have done so far, and I cant seem to see anything I have missed out on.. could anyone be kind enough to guide me?

Also on a side note: Instantiation of a module in verilog

I was trying to instantiate my module in a if statement, so I tried outside of the if statement in a always @(posedge clk) block, and I get the error

HDL syntax error at seqalign.v(88) near text "("; expecting ";"

First off, do not use assign inside an always block : stackoverflow.com/q/23687172/1959732 — Greg
Remove the implementation and stay with empty module alone and try again. — Eugene Sh.
Eugene Sh: I tried your suggestion and it did work. It compiled fine. So my problem lies in the fact that I am trying to instantiate the module in a code block containing if and always etc.. I have uploaded my code to pastebin. pastebin.com/2SmkpuDN. Please note: It is NOT complete so the logic is not wholly there. Can you or anyone indicate to me how to go about using a maximum module inside the if / always block? Do i have to use a generate block? — Melvin

Unn Unn · Accepted Answer · 2015-01-27T18:21:48

Looking over the code you posted in your comment, the issue is from instantiating your module inside your always @(posedge clk) block on line 70. You never instantiate modules inside of procedural blocks (always, initial, etc).

As Verilog is a Hardware Descriptive Language, you have to be in the mindset of designing hardware when writing your code. Module instantiation is like soldering a chip onto a PCB, at design time you either do it, or you dont, and that component stays there for all time. You dont say, well, I want this chip here some of the time, but take it off the PCB when the system gets into these states. In your code, you conditionally instantiate your module if state is 3. However, state changes over time. So that is akin to saying, when the register containing state reads 3, place down this chip into the system, otherwise, it doesnt exist and take it out. On a code level, think of instantiated modules as their own procedural blocks, just as you dont put always inside of other always, dont put modules in always blocks (of course, module definitions/declarations can have always blocks inside them).

Modules are persistent and compile time constant, so you can use generates to conditionally instantiate modules at compile time (ie, decide whether or not to include the module in the design when building the system). But in your code, you are conditionally instantiating at simulation time, which is not allowed as described above.

You can do one of two things to solve your problem. One would be to move your task from your submodule maximum into the systolic_PE module and use it to get the maximum of your variables tby calling it (line 123 would become something like tempA <= convert(.a(0), .b(diag+match)); with a and b added as inputs to your task). Or, instantiate the module outside the always block, but youll need to change your task to be a procedural block like you have in the actual post.

Verilog module instantiation

1 Answers