I am getting error in the verilog code for stopwatch in Altera DE1

2
votes

I am getting error in verilog code while compiling using Quartus II as under

Error (10119): Verilog HDL Loop Statement error at DE1_SOC_golden_top.v(313): loop with non-constant loop condition must terminate within 250 iterations

Line 313 is #50 clock = ~clock;

code for the test bench module is 

module test;

 // Inputs
 reg clock;
 reg reset;
 reg start;

 // Outputs
 wire [3:0] d0;
 wire [3:0] d1;
 wire [3:0] d2;

 // Instantiate the Unit Under Test (UUT)
 stopwatch uut (
  .clock(clock), 
  .reset(reset), 
  .start(start), 
  .d0(d0), 
  .d1(d1), 
  .d2(d2)
 );

initial
  begin
   clock = 0;
    forever
     #50 clock = ~clock;
  end

 initial begin
  // Initialize Inputs
  reset = 0;
  start = 0;

  // Wait 100 ns for global reset to finish
  #100;
  reset = 1;
  #100;
  reset = 0;
  #100;
  start = 1;
  // Add stimulus here
 end

endmodule

Any suggestions for rectifying the same. I am generating a 0.1 second delay..

2
verilog
Quartus is synthesis. You typically only simulate with a testbench as they often contain unsynthesizable code (like forever loops). – Greg
ok you mean I should be doing compilation with the original code and only test code for simulation.. right. – Nyom Kal

2 Answers

0
votes

You can rewrite the line as below to clear the error

clock = #50 ~clock;
0
votes
initial
  begin
   clock = 0;
    forever
     #50 clock = ~clock;
  end

This method of generating a clock only works in simulation workflows. For synthesis, you need to connect an actual clock signal to the FPGA.