verilog- assign statement reg to output variable not being assigned

Question

I am attempting to use an FPGA as a shift register to some LEDs with pwm, but ran into an error while trying to assign a reg containing the value shifted in to an output variable. When I upload it to the FPGA(i'm using the mojo by embedded micro), it does nothing. when I use the simulator, it reports that all of the output variables are never assigned and have the value of X, while all the other variables inside of the module work just fine. here is my code for the shifting module:

module shifting(
    input clk,
    input shiftingpin,//data to be shifted in
    input rst,
    output done,
    output [3:0]data//pwm compare value output
    );
reg [2: 0] ctr_d, ctr_q;
reg don;
reg [3:0]datas;
always @(*) begin
     if(ctr_q == 3'b100) begin
        ctr_d[2:0] = 3'b0;
        don = 1'b1;
     end else begin
       ctr_d = ctr_q + 1'b1;
        don = 1'b0;
     end
end
always @(posedge clk) begin
     datas[ctr_q] = shiftingpin;// assign value to the output
    if (rst) begin
        ctr_q <= 1'b0;
    end else begin
        ctr_q <= ctr_d;
    end
end
assign data = datas;
assign done = don;
endmodule

done tells the containing module when to update and assign the value to pwm.

Can you add your tb code that simulates the inputs? (Also note that the line that stores the shiftingpin to datas should be non-blocking: datas[ctr_q] <= shiftingpin; ) — Unn

Morgan Morgan · Accepted Answer · 2014-10-12T06:14:33

If I understood the question correctly you have a syntax error when trying to drive ports from within always blocks.

When declaring ports they are typically wire by default which can only be driven by ports or assign. Resulting in the code below

module shifting(
    input        clk,
    input        shiftingpin,
    input        rst,
    output       done,
    output [3:0] data
);
reg           don; 
reg [3:0]     datas;
assign done = don;    
assign data = datas;

Solution

The solution is to define ports as reg, logic is preferred if you can support System Verilog. logic will effectively switch between wire and reg as required to make refactoring code easier.

module shifting(
    input             clk,
    input             shiftingpin,
    input             rst,
    output reg        done,
    output reg  [3:0] data
);
always @(posedge clk) begin
 data[ctr_q] <= shiftingpin; // <-- data port used directly
//...

NB: shift registers can be done with just

always @(posedge clk) begin
  datas[3:0] <= {datas[2:0], shiftingpin};

verilog- assign statement reg to output variable not being assigned

1 Answers

Solution