Verilog assign statement result check

Question

new to Verilog (well, SystemVerilog really, but I found that for the very basic keywords like assign and initialize I am able to learn from Verilog resources as well). I am following example 2 on this link chipverify example 2. It's simple so I'll write it down. I feel as if they've made a mistake, but since I am a newbie it's hard to know if my feeling is correct or not.

module xyz (input [3:0] x, //let x='hC or x='b1100 for this example's purposes
            input       y, //y is a 1bit scalar y='h1 = 'b1
            output [4:0] z);
//case 8
assign z = {3{y}};

endmodule

For case 8, they are saying that z will result in z='b00111. I don't think it's correct! Following their case 3, where z only got bits [4:1] assigned,it stated that the reaming bit will be undriven and thus result in high impedance Z. Shouldn't the result of case 8 then be z ='bZZ111 and not z='b00111?

Let me know, thanks! =)

Hiroto Kagotani Hiroto Kagotani · Accepted Answer · 2020-01-20T06:04:26

From section 10.7 (Assignment extension and truncation) in IEEE Std 1800-2017 (the SystemVerilog standard),

When the right-hand side evaluates to fewer bits than the left-hand side, the right-hand side value is padded to the size of the left-hand side.

In your case, {3{y}} is an unsigned value, so it is 0-padded to 5 bits, that is 5'b00111, and then assigned to z.

Verilog assign statement result check

1 Answers