== operator in assign statement (Verilog)

Question

I am trying to understand some of the System Verilog syntax. I was struggling to finish an assignment and I came across this solution, but I do not understand why it works.

localparam int lo = w;
uwire [n:0] lo_bits, hi_bits;
assign answer = lo_bits == nlo ? lo_bits + hi_bits : lo_bits;

This is not exactly what I have in my code, but my question is the following: Why can't I rewrite this to a simple if-else block as such?

if (lo == lo_bits)
    assign answer = lo_bits + hi_bits;
else
    assign answer = lo_bits;

Verilog complains that lo_bits is a uwire and I cannot compare it with lo, but then why is it allowed in the example above? Aren't these two assignments equivalent?

Thank you very much for your help!

dave_59 dave_59 · Accepted Answer · 2019-10-08T18:32:51

The difference is structural/declarative context versus procedural context. When you use an if clause in a declarative context (in this case it is at the same top level where you declare your wires and variables), it is considered a conditional generate construct (See Section 27.5 in the 1800-2017 LRM). This means the condition gets evaluated before simulation starts and must contain only constant expressions and no signals that can change during simulation. lo is a constant parameter, but not lo_bits.

If you want to use a procedural if, it needs to be inside a procedural block of code instantiated by always/initial blocks.

logic [n:0] answer;
always_comb
  if (lo == lo_bits)
    answer = lo_bits + hi_bits;
else
    answer = lo_bits;

== operator in assign statement (Verilog)

1 Answers