Generate block inside case statement in verilog or system verilog

Question

Is there a way in Verilog or SystemVerilog to insert generate statement inside case statement to generate all the possible input combinations. For example a typical use case would be for a N:1 mux.

case(sel)
  generate
    for(i = 0; i < N; i += 1)
      i: out = q[i];
  endgenerate
endcase

I tried this, but the tool gives error. An alternate syntax is available which is

out <= q[sel];

But, my tool is not understanding this(the mux is fully decoded) and generating combinational loops. I can use if statement to get the expected mux. But, I was wondering if there was a better way to do it.

How would your first code work? You want to assign N values to 1-bit wide bus in 1 clock cycle. On the other hand, your second syntax is exactly the same as provided by Altera on their website, so it should work just fine. Probably other logic cause generation of combinational loops. — Qiu
My design is wire [WIDTH-1:0] q[NO_PAGES-1]. The q output is coming from different memory pages. I need to route particular page output based on page select signal (which is select line of mux). It is expected to be pure combinatorial logic. Actually I'm using synplify_pro, which is giving me this issue. — siu

Tudor Timi Tudor Timi · Accepted Answer · 2014-09-15T16:36:54

You can't mix a for and a case like that. If you're just trying to write a multiplexer, have a look at this older question: How to define a parameterized multiplexer using SystemVerilog

The only difference there is that the select signal is supposed to be onehot encoded. For your case you would have:

always_comb begin
out = 'z;
for (int i = 0; i < N; i++) begin
  if(sel == i)
    out = q[i];
end

Generate block inside case statement in verilog or system verilog

1 Answers