Conditional code in Verilog in a generate loop

Question

I am trying to encode conditional behavior for Verilog statements in a generate loop. For example, the code below returns an error.

module <something> (out);

parameter [4:0] someParam = 0;
output [5:0] out;
genvar l, m;

for(l=0; l<5; l=l+1) begin:STAGE_1
  m = 0;  
  if(someParam[l] < 2)   
    m = l+2;
  else begin  
    m = l-2;
  end
  if (m>16) assign out[l] = 1'b0;  
  else assign out[l] = 1'b1;   
end
endmodule

The problem is that the variable m is not a constant and the code errors out. Is there any way I can use compile time variable inside a generate statement which would allow some functionality like the variable m above?

Thanks.

Your code is missing one end. There are two begins but only one end — Ari
There are too algorithmic errors to give a property answer. (someParam[l] < 2) is always false, (m>16) is always false, out[5] is never assigned. No mater the value of someParam out will always be 5'bz1111. — Greg

Razko Razko · Accepted Answer · 2014-09-22T10:22:00

I didnt understand what you intended to calculate due to some errors in your code.

In general, for you to use a parameter in a statement you can use an always block with a if statement as following:

module <something> (out);
parameter [4:0] someParam = 0;
output out;      // in this case out is only one bit. it can be more of course.
integer l,m;     // no need for genver when not using generate

always (*) begin
  m = 0;
  for (l=0; l<5; l=l+1) begin:STAGE_1
    if (someParam[l] == 1'b1) // nothing good comes for checking if a bit is less then 2
      m = m+1;                // just counting bits in someParam. doing +-2 does not make sense.
  end
  if (m >= 3)
     out = 1'b1;
  else
     out = 1'b0;
end

The above is a majority function.

Good luck

Conditional code in Verilog in a generate loop

1 Answers