Sorry for such a general question. I have experience in Verilog but new to FPGA and Quartus II. I use Quartus II to try to compile a design and to see how much logic the design uses. I followed the quick tutorial of Quartus II by Altera. http://www.altera.com/literature/manual/mnl_qts_quick_start.pdf
However, after the step of analysis and synthesis, I noticed there is no logic utilization at all. Only the two Input pins of top module could be seen.
The top module of my design is
RiSC(clk,reset)
Naturally, after compilation, there is still nothing but two pins.
Have you ever met this problem? Could you give me some hint? The design contains hundreds of lines of verilog codes so there should be logic utilization.
Thanks!
