How Quartus optimize your circuit?

Question

I am using Altera FPGA to design some circuits. During synthesis with Quartus, I found that if I give different input signals (my input signal is a .hex file that stored a bunch of instructions), the logic elements consumption is different.

For example, if my instructions require most of modules, the logic consumption is big. However, if I make the .hex file only utilizes a certain module, the logic consumption is much less.

Is that the synthesis tool automatically optimize the module if you didn't plan to use it?

My input signals is actually store in a instruction memory, my processor executes one instruction per clock cycle. I wrote instructions in a .hex file, then in the instruction memory module, I use $readmemh("primenum.hex",Instruction_Memory); to read instructions from .hex file.

Answer 1

If some of your logic has no fan-out i.e. it is not driving any other logic then it will be removed during synthesis.

If there is no logic to modify the state of your instruction memory then it will be implemented as a ROM. Since the instruction memory is driving the logic to execute specific instructions, the synthesis tool will remove any module that is not driven by the set of instructions in your instruction memory.

To prevent this from happening, you need to connect your design to some I/O which can modify the state of your instruction memory. If the set of instructions to be executed is unknown at synthesis time then the synthesis tool will assume that the instruction memory can take any state which means that it could end up driving the logic of any possible instruction (module).