Comparing bits from std_logic_vector

Question

attempt #1

overflow_next <= (op1_shifted(word_width - 1) = op2(word_width - 1)) and (result_var(word_width - 1) /= op2(word_width - 1));

Error (10327): VHDL error at alu.vhd(99): can't determine definition of operator ""="" -- found 0 possible definitions

Error (10327): VHDL error at alu.vhd(99): can't determine definition of operator ""/="" -- found 0 possible definitions

attempt #2

overflow_next <= ((op1_shifted(word_width - 1) = '0') and (op2(word_width - 1) = '0') and (result_var(word_width - 1) = '1')) or ((op1_shifted(word_width - 1) = '1') and (op2(word_width - 1) = '1') and (result_var(word_width - 1) = '0'));

Error (10327): VHDL error at alu.vhd(99): can't determine definition of operator ""="" -- found 0 possible definitions

All signals and variables are std_logic_vector except word_width which is an integer generic. What's the problem here? I can compare standalone std_logic signals but not parts of std_logic_vector signals? Is there any workaround if what I'm trying to do is impossible?

Answer 1

I suspect the error report is misleading and you need to properly construct a conditional signal assignment statement, such as:

overflow_next <= '1' when (op1_shifted(word_width - 1) = op2(word_width - 1)) and (result_var(word_width - 1) /= op2(word_width - 1)) else '0';