VHDL: Subtract std_logic_vector

0
votes

I am developing a code on VHDL and I need to make subtraction operation on std_logic_vector. I tried to define and use the following libraries:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;

then I defined signals like:

signal r0,r1,r2,r3,r4,r5,r6,r7: STD_LOGIC_VECTOR (19 DOWNTO 0);

then I wanted to do the following subtraction:

        r0 <= r0(16 downto 8) - r0(7 downto 0);

But it gives me error on the - operator. The error says:

Error (10327): VHDL error at euclidian_vhd_hls.vhd(84): can't determine definition of operator ""-"" -- found 0 possible definitions

Please help me to solve this issue.

Thanks a lot.

2
signal-processingvhdl

2 Answers

0
votes

I found an answer to use the following syntax:

r0 <= std_logic_vector(unsigned(r0(16 downto 8)) - unsigned(r0(7 downto 0)));

I guided to this solution by this Stackoverflow question

0
votes

I think you logic doesn't work, becouse you apply r0 onn r0, it infinity loop. you need state it on process with rising or falling edge