Compile error with operator ""&""" vhdl

Question

I'm programming VHDL and I have a problem when compiling the testbench. Get the following error:

Error (10327): VHDL error at comparador_12_tb.vhd(56): can't determine definition of operator ""&"" -- found 0 possible definitions

Code

library ieee;
use ieee.std_logic_1164.all;

entity comparador_12 is
port( num1 : in std_logic_vector(3 downto 0);  
      num2 : in std_logic_vector(3 downto 0);
        clock : in std_logic;
      menor : out std_logic;   
      igual : out std_logic;   
      mayor : out std_logic
       );
end comparador_12;

architecture behavioral of comparador_12 is
begin
    process(num1,num2)
        begin    
            if (num1&num1&num1 > num2&num2&num2 ) then  
                menor <= '0';
                igual <= '0';
                mayor <= '1';
            elsif (num1&num1&num1 < num2&num2&num2) then    
                menor <= '1';
                igual <= '0';
                mayor <= '0';
            else    
                menor <= '0';
                igual <= '1';
                mayor <= '0';           
        end if;
    end process;   
end behavioral;

Testbench

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY comparador_12_tb IS
END comparador_12_tb;

ARCHITECTURE behavioral OF comparador_12_tb IS
-- constants                                                 
-- signals                                                   
SIGNAL igual : STD_LOGIC;
SIGNAL mayor : STD_LOGIC;
SIGNAL menor : STD_LOGIC;
SIGNAL num1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL num2 : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal clk : std_logic := '0';
constant clk_period : time := 20 ns;
signal x,y : std_logic;

COMPONENT comparador_12
    PORT (
    igual : BUFFER STD_LOGIC;
    mayor : BUFFER STD_LOGIC;
    menor : BUFFER STD_LOGIC;
    num1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    num2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
    );
END COMPONENT;

BEGIN
    uut : comparador_12
    PORT MAP (
-- list connections between master ports and signals
    igual => igual,
    mayor => mayor,
    menor => menor,
    num1 => num1,
    num2 => num2
    );

clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;  
        clk <= '1';
        wait for clk_period/2;  
end process;

tb : process
begin
        num1 <= "1001";
        num1 <= "1100";
        num1 <= "0100";
        num2 <= "1110";
        num2 <= "1101";
        num2 <= "1000";
        x <= num1&num1&num1;
        y <= num2&num2&num2;
    wait for 10 ns;
end process;            
END behavioral;

The VHDL compiler can't find an overload for "&" which takes 3 4-bit inputs and makes a 1-bit output, because the result (in "X" and "Y") will be 12 bits. What do you want X and Y to be? — user_1818839

scary_jeff scary_jeff · Accepted Answer · 2015-09-25T15:01:14

Looking at the following signal declarations in your test bench:

signal num1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal x,y : std_logic;

And the code:

x <= num1&num1&num1;

& is the concatenation operator. In this case, you are concatenating a 4-bit vector with itself, creating a 12-bit vector. You are then assigning the result to a single-bit std_logic signal. I'm not sure what you would expect to happen here, but this is the reason for the error.

Compile error with operator ""&""" vhdl

1 Answers