Assign signal in many processes

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I try to learn VHDL language I don't understand a strange thing. This thing refers to the signals from an architecture.

My question is: Why we can't assign bit signal, integer signal, etc in more than one process/ concurrent assign. But I saw, we can assign in more than one process Std_logic_vector signal and Std_logic signal.

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vhdl
"But I saw, we can assign in more than one process Std_logic_vector signal and Std_logic signal." Please show us the code where you think that is correctly used. – Oldfart
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"It is an error if, after the elaboration of a description, a signal has multiple sources and it is not a resolved signal.", IEEE Std 1076-2008 6.4.2.3 Signal declarations. "The resolution function associated with a resolved signal determines the resolved value of the signal as a function of the collection of inputs from its multiple sources.", 4.6 Resolution functions. The resolution function for std_logic or std_logic_vector (named resolved) is found in the std_logic_1164 package body. Restrictions on multiple drivers can be target device limited and defined by synthesis tools. – user1155120

1 Answers

1
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It is an error if, after the elaboration of a description, a signal has multiple sources and it is not a resolved signal.

IEEE Std 1076-2008 6.4.2.3 Signal declarations.

The resolution function associated with a resolved signal determines the resolved value of the signal as a function of the collection of inputs from its multiple sources.

4.6 Resolution functions.

The resolution function for std_logic or std_logic_vector (named resolved) is found in the std_logic_1164 package body.

Restrictions on multiple drivers can be target device limited and defined by synthesis tools.

made @user1155120 's comment a community wiki answer