How to put desired inputs for VHDL simulation (force Command)

Question

The Following is the VHDL code for a counter using D flip-flops. Here we are assuming the flip-flops are positive edge triggered.

Inside the architecture, I declared Q (present state) and D as a 4-Bit logic vector.

I assigned all the outputs (Z0 to Z7) and D signal values to match the logic expressions determined by the minimum input equations for the counter and flip-flops respectively.

At the end of the code a process is called to simulate the behavior of clear (ClrN) and clock (CLK)

My Question:

The code works properly but I am facing an issue with the Simulation of the test bench.

In the simulation we need to show circuit started out with the state 1000 and it then goes through each state in the correct order.

In Short: How do i show the signals Q and D in the simulation.
This is the part i am not sure on how to do.

I was told to use the force commands to set the desired inputs.

For Example:

force ClrN 0 0, 1 20  
force CLK 1000 0  
force CLK 0 0, 1 40 -repeat 80

But i am not sure where and how to use it.

Below is the VHDL Code:

library IEEE;  
use IEEE.STD_LOGIC_1164.ALL;

entity counter is
port (CLK, ClrN : in std_logic;  
        Z0 : out std_logic;  
        Z1 : out std_logic;  
        Z2 : out std_logic;  
        Z3 : out std_logic;  
        Z4 : out std_logic;  
        Z5 : out std_logic;  
        Z6 : out std_logic;  
        Z7 : out std_logic);  
end counter;

architecture Behavioral of counter is

signal Q: std_logic_vector(0 to 3);
signal D: std_logic_vector(0 to 3);

begin

u1: process(Q)

begin

Z0 <= Q(0) and not Q(1) and not Q(3);
Z1 <= Q(0) and Q(1);
Z2 <= not Q(0) and Q(1) and not Q(2);
Z3 <= Q(1) and Q(2);
Z4 <= not Q(1) and Q(2) and not Q(3);
Z5 <= Q(2) and Q(3);
Z6 <= not Q(0) and not Q(2) and Q(3);
Z7 <= Q(0) and Q(3);

D(0) <= not Q(1) and not Q(2);
D(1) <= not Q(2) and not Q(3);
D(2) <= not Q(0) and not Q(3);
D(3) <= not Q(0) and not Q(1);
end process u1;


u2: process(CLK,ClrN)  
begin  
if ClrN = '0' then  
Q <= "1000";  
elsif Rising_Edge (CLK) then  
Q <= D;  
end if;  
end process u2;  

end Behavioral;

The following is my VHDL test bench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS 

    COMPONENT counter
    PORT(
         CLK : IN  std_logic;
         ClrN : IN  std_logic;
         Z0 : OUT  std_logic;
         Z1 : OUT  std_logic;
         Z2 : OUT  std_logic;
         Z3 : OUT  std_logic;
         Z4 : OUT  std_logic;
         Z5 : OUT  std_logic;
         Z6 : OUT  std_logic;
         Z7 : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal CLK : std_logic := '0';
   signal ClrN : std_logic := '0';

    --Outputs
   signal Z0 : std_logic;
   signal Z1 : std_logic;
   signal Z2 : std_logic;
   signal Z3 : std_logic;
   signal Z4 : std_logic;
   signal Z5 : std_logic;
   signal Z6 : std_logic;
   signal Z7 : std_logic;

   -- Clock period definitions
   constant CLK_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: counter PORT MAP (
          CLK => CLK,
          ClrN => ClrN,
          Z0 => Z0,
          Z1 => Z1,
          Z2 => Z2,
          Z3 => Z3,
          Z4 => Z4,
          Z5 => Z5,
          Z6 => Z6,
          Z7 => Z7
        );

   -- Clock process definitions
   CLK_process :process
   begin
        CLK <= '0';
        wait for CLK_period/2;
        CLK <= '1';
        wait for CLK_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin        
--      -- hold reset state for 10 ns.

      wait for 10 ns;   

        ClrN <= '1'; 

     wait;
   end process;

END;

Where and how do I add the Q and D signals to my test bench in order to get the simulation that shows the circuit started out with the state 1000 and it then goes through each state in the correct order. and do i even use force command?

What simulator are you using? There's normally a design hierarchy browser of some sort that allows you to add signals in the design to the waveform window, is that what you're asking for? — scary_jeff
Also, your force commands seem somewhat unconventional; you're already assigning ClrN and CLK in the test bench itself, so it's not clear why you would then also set them to potentially conflicting values using the 'force' command. — scary_jeff
"your force commands seem somewhat unconventional" i was suggested to used it, but i didnt know how to. In order to get an output on the simulation i already assigning ClrN and CLK in the test bench — Allen Mathew

FritzDC FritzDC · Accepted Answer · 2017-04-04T06:12:33

One way to document what happens in the simulation (in addition to the waveform) is to write the desired signals into output (like printf in c) or to file (like fprintf).

To do this, first include textio package:

use std.textio.all;
use ieee.std_logic_textio.all;

and then amend you process:

u2: process(CLK,ClrN)  
  file f0 : text is out "output.txt";
begin  
  if ClrN = '0' then  
    Q <= "1000";  
  elsif Rising_Edge (CLK) then  
    --pragma translate_off
    write(output, "Q:" & to_string(Q) & " D:" & to_string(D) & lf);
    write(f0, "Q:" & to_string(Q) & " D:" & to_string(D) & lf);
    --pragma translate_on
    Q <= D;  
  end if;  
end process u2;

The pragmas are not absolutely necessary, but they are a good habit to add to whatever non-synthesizable code inside a module that is meant for synthesis.

In your example, force should be used not.

How to put desired inputs for VHDL simulation (force Command)

1 Answers