VHDL - why do we need to declare signals for processes?

Question

Just revisiting some VHDL and I was wondering inside processes for example, why do we need to declare a signal for a clock for example? Then later on in the code assign it to the port from the entity...

EXAMPLE VHDL:

signal clk_int: std_logic := '1';

BEGIN
clkgen: process(clk_int)
begin
clk_int <= not clk_int after 50ns
end process ckgen

ck_l <= clk_int;

In this example ck_l is a physcial port from the d flip flop yet we create and mess around with clk int then return the value to ck

youR.Fate youR.Fate · Accepted Answer · 2014-03-23T23:15:50

The reason is that the port ck_l in this case is probably declared with direction out, so It cannot be read from. If you want to read it, like you would need to if you want to have a process that is sensitive to it, you need to use a signal or declare the port as inout or buffer.

VHDL - why do we need to declare signals for processes?

1 Answers