How to multiply by 2 a 32 bit signed std_logic_vector in VHDL

Question

We have a type which is an array of 32 bit "std_logic_vector" of size 3, which is defined in the following way:

subtype scalar is std_logic_vector(31 downto 0);
type vector_nd is array (natural range <>) of scalar;
subtype vector_3d is vector_nd(2 downto 0);

We have a signal of type "vector_3d" which we want to multiply by 2 and put the result in a signal of type "scalar":

signal v_normal_out_sig := vector_3d;
signal mult1_in1_sig    := scalar;
--...
mult1_in1_sig <= 2*signed(v_normal_out_sig(0)) when cau_state = st_cycle18;

When we compile it we get the error:

No feasible entries for infix operator "*".

What is the right way to implement what we want? We are using the following libraries:

ieee.std_logic_1164.all
ieee.std_logic_arith.all
ieee.std_logic_unsigned.all

You could simply left-shift your v_normal_out_sig(0) signal by 1 bit to achieve a multiplication by 2. Consider using the functions provided by the numeric_std library (i.e. SHIFT_LEFT). — simon
@simon, those are signed numbers, I can't just Shift Left as I'll lose the sign bit. We implemented our own "shift left", shown in the answer. — SIMEL
Ilya, most languages have bit shift operations that preserve the sign (not sure about VHDL). — NominSim
The SHIFT_LEFT function takes care of that. However, your own function should also be fine. I'd still suggest making use of the numeric_std functions for cleaner and (arguably) better readable code. — simon

SIMEL SIMEL · Accepted Answer · 2012-08-24T13:30:23

What we did eventually is the fallowing:

mult1_in1_sig <= v_normal_out_sig(0)(31) & v_normal_out_sig(0)(29 downto 0) & '0' when cau_state = st_cycle18;

And test gave the right results for both positive and negative numbers.

How to multiply by 2 a 32 bit signed std_logic_vector in VHDL

1 Answers