VHDL type conversion - found 4 possible definitions

Question

I am trying convert two std_logic bits to an integer as follows

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY TEST IS
    PORT (sw1, sw0  :   IN      std_logic;
          x         :   OUT     integer RANGE 3 DOWNTO 0);
END ENTITY TEST;

ARCHITECTURE dflow OF TEST IS
    SIGNAL mes_sel : integer RANGE 3 DOWNTO 0;
BEGIN
    mes_sel <= to_integer(unsigned(std_logic_vector(SW1 & SW0)));
    x <= mes_sel;
END ARCHITECTURE dflow;

but the compiler does not like the mes_sel assignment. I get the following compiler error message:

Error (10327): VHDL error at Q4.vhd(92): can't determine definition of operator ""&"" -- found 4 possible definitions

Can I not concatenate 2 bit of std_logic to a vector and then convert? Or is it something else? regards D

What does it not like? Did it, like, give an error message or something? (Incidentally you can form an unsigned directly from two std_logics, there should be no need to go via std_logic_vector) — user_1818839

user_1818839 user_1818839 · Accepted Answer · 2016-01-30T13:17:22

The error message tells you roughly what's wrong, and it's not a problem with the assignment.

GHDL gives a better diagnosis:

ghdl -a test.vhd
test.vhd:13:57: can't resolve overload for operator "&"
test.vhd:13:57: possible interpretations are:
../../src/ieee/numeric_std.v93:66:18: array type "signed"
../../src/ieee/numeric_std.v93:65:20: array type "unsigned"
../../src/ieee/std_logic_1164.v93:69:30: array type "std_logic_vector"
../../src/ieee/std_logic_1164.v93:54:31: array type "std_ulogic_vector"
ghdl: compilation error

VHDL allows overloaded operators, distinguishable by the types of their arguments (in this case, std_logic) and their return types, (in this case ... well... what?)

There are apparently 4 types which have a std_logic_vector() type conversion function declared on them, as well as a & operator taking two std_logic arguments; and ghdl (unlike whatever tool you're using) helpfully lists them.

In such cases, VHDL (unlike some other languages) insists that you pick one, rather than arbitrarily making a hidden (and possibly wrong) choice for you.

You can do this with a type mark. As you actually want an unsigned, the obvious choice is unsigned'() (note the "'" symbol, also used for attributes).

mes_sel <= to_integer(unsigned'(SW1 & SW0));

Note that if VHDL allowed anything simpler, like to_integer(SW1 & SW0) it would be positively dangerous as there is nothing to distinguish between signed and unsigned conversions, making the conversion at least non-obvious, and quite possibly wrong.

VHDL type conversion - found 4 possible definitions

1 Answers