VHDL incrementer "add one"

Question

I do not how to write the truth table of this question so I can not do this question, can anyone help me understand what this question let us do? Thank you very much.

An incrementer is a combinational circuit that adds ONE to an input unsigned integer (X). The output unsigned integer (Y) has the same number of bits as the input. There is no output carry, an input string of all ‘1’s increments to all ‘0’s.

a) Write the Full-Adder Equations with inputs A0 , B0 and C0 . (aka Cin)

b) substitute with A0 = X0 , B0 = ‘0’ and C0 = ‘1 and then simplify.

c) Write the Full-Adder Equations with inputs Ai , Bi and Ci.

d) substitute with Ai = Xi , and Bi = ‘0’ and then simplify.

e) Consider a 6-bit Ripple-Adder that has A = X, B = 0 and Cin = ‘1’. Clearly this would be an incrementer. Draw a Structural Diagram of a 6-bit incrementer using the simplified circuits that you have derived in (b) and (d). (Label all instances and signals.)

VHDL can be used to model the time delay of individual gates. Please refer to your lecture notes for the BNF syntax of signal assignment. The delay format is used by simulators but is ignored by synthesizers. Use the following statements to code 2-input gates and inverters.

Code 2-input AND gates using statements with 4 ns delays,Y <= A and B after 4 ns;

Code 2-input XOR gates using the statements with 4 ns delays,Y <= A xor B after 4 ns;

Code inverters using the statements with 1 ns delays,Y <= not A after 1 ns;
Make a new directory called PLA03 and then start a new ModelSim project called PLA03.Always put Entity/Architectures in their own source files and use the Entity name as the filename.

f) Write an Entity/Architecture for your simplified circuit in (b). Name the Entity IncStage0

g) Write an Entity/Architecture for your simplified circuit in (d). Name the Entity IncStageI

h) Write an Entity named Inc6 and a Structural Architecture for your 6-bit Incrementer in (e). Remember to declare the inputs and outputs as unsigned.

library ieee;
use ieee.std_logic_1164.all;  
Use ieee.numeric_std.all;
Entity IncStage0 is
  port(
       X:in unsigned;
        S: out unsigned;
        Cout: out unsigned);
End Entity IncStage0;
Architecture behaviour of IncStage0 is
Begin
  S <= not X after 4 ns;
  Cout <= X;
End Architecture behaviour;

library ieee;
use ieee.std_logic_1164.all;  
Use ieee.numeric_std.all;
Entity IncStageI is
  port(
      X:in unsigned;
      Cin: in unsigned;
      S: out unsigned;
      Cout:out unsigned);
End Entity IncStageI;
Architecture stageI of IncStageI is
Begin
  S <= X xor Cin after 4 ns;
  Cout <= X and Cin after 4 ns;
End Architecture stageI;

library ieee;
use ieee.std_logic_1164.all;  
Use ieee.numeric_std.all;
Entity Inc6 is
  port( 
        X:in unsigned (5 downto 0);
        Y:out unsigned (5 downto 0));
End Entity Inc6;
Architecture behaviour of Inc6 is
  signal C:unsigned (5 downto 0);
  Component IncStage0
     port(
       X:in unsigned;
        S: out unsigned;
        Cout: out unsigned);
  End Component ;
 Component IncStageI
     port(
      X:in unsigned;
      Cin: in unsigned;
      S: out unsigned;
      Cout:out unsigned);
  End Component;
Begin
  I0: IncStage0
    port map(X=>X, S=>Y, Cout=>C);
  I1: IncStageI
    port map(X=>X, S=>Y, Cout=>C,Cin=>C);
  I2: IncStageI
    port map(X=>X, S=>Y, Cout=>C,Cin=>C);
  I3: IncStageI
    port map(X=>X, S=>Y, Cout=>C,Cin=>C);
  I4: IncStageI
    port map(X=>X, S=>Y, Cout=>C,Cin=>C);
  I5: IncStageI
    port map(X=>X, S=>Y, Cout=>C,Cin=>C);
End Architecture behaviour;

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity TBInc6 is
End Entity TBInc6;
Architecture rtl of TBInc6 is
  signal tbX,tbY: unsigned(5 downto 0);
Begin
DUT: Entity work.Inc6 port map(X => tbX, Y => tbY);
Main: Process
  Begin
    for i in 0 to 63 loop
      tbX <= to_unsigned(i,6);
      wait for 30 ns;
    end loop;
    Wait;
  End Process Main;
End Architecture rtl;

Answer 1

After fixing the delay in incStage0 for the NOT (should be 1 ns, not 4 ns),and changing the unconstrained subtype indications for type unsigned to type std_logic (incStage0, incStageI and their component declarations), as well as restoring the indexes for I0 through I5 you removed in your questions 5th edit and then you get:

Which looks correct compared to your instructor's supplied waveform.

Note it's hard to hit a moving target, every time you change your question the answer changes. A good indication you should be asking separate questions.

You could modify inc6 to declare signal C as:

architecture behaviour of Inc6 is
  signal C:unsigned (4 downto 0);
  component IncStage0
     port(
       X:in std_logic;
        S: out std_logic;
        Cout: out std_logic);
  end component ;

And change the I5 instantiation:

  I5: IncStageI
    port map(X=>X(5), S=>Y(5), Cout=> open, Cin=>C(4));

Because you're using name association in the interface list you could simply:

  I5: IncStageI
    port map(X=>X(5), S=>Y(5),Cin=>C(4));

leave off mention of the carry out.

addendum

Is that means I should change every type unsigned to std_logic or std_logic_vector?But if I try to change everything to std_logic, it says no feasible entries for to_unsigned which is in part h code, how to fix that?

No. unsigned is an array type. From package numeric_std (-2008):

 type UNRESOLVED_UNSIGNED is array (NATURAL range <>) of STD_ULOGIC;

 subtype UNSIGNED is (resolved) UNRESOLVED_UNSIGNED;  

-1987, -1993, -2002:

  type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;

While in package std_logic_1164 (-2008):

  subtype STD_LOGIC is resolved STD_ULOGIC;

-1987, -1993, -2002:

 SUBTYPE std_logic IS resolved std_ulogic;

In all revisions of the VHDL standard the base type of std_logic is std_ulogic, which is also the base type of the element type of the array type unsigned.

This means you can connect elements of an unsigned (representing bits) to std_logic signals, including ports. The element base type of both is std_ulogic which is a multi value representation of a bit providing both weak and strong logic level forcing and meta values representing the value of a bit:

TYPE std_ulogic IS ( 'U',  -- Uninitialized
                     'X',  -- Forcing  Unknown
                     '0',  -- Forcing  0
                     '1',  -- Forcing  1
                     'Z',  -- High Impedance
                     'W',  -- Weak     Unknown
                     'L',  -- Weak     0
                     'H',  -- Weak     1
                     '-'   -- Don't care
                   );

(Also see IEEE Std 1076-2008, 16.8.2.2 The STD_LOGIC_1164 values - "The logical values '1', 'H', '0', and 'L' of type STD_ULOGIC are interpreted as representing one of two logic levels, where each logic level represents one of two distinct voltage ranges in the circuit to be synthesized.", the one of two logical values, a bit).

As you have undoubtedly discovered you can't connect an array type to a scalar type. incStage0 (I0) and inStageI (I1, I2, I3, I4 and I5) represent bits:

h) Write an Entity named Inc6 and a Structural Architecture for your 6-bit Incrementer in (e). Remember to declare the inputs and outputs as unsigned.

In the code snippets showing the use of an open for an actual on I5 the declaration for C is shown as unsigned and I5 is shown using indexed names (elements on an array object). In addition to declaring the bit slice elements of inc6 as std_logic:

entity IncStage0 is
  port(
       X:in std_logic;
        S: out std_logic;
        Cout: out std_logic);

Entity IncStageI is
  port(
      X:in std_logic;
      Cin: in std_logic;
      S: out std_logic;
      Cout:out std_logic);

  component IncStage0
     port(
       X:in std_logic;
        S: out std_logic;
        Cout: out std_logic);
  end component ;
 component IncStageI
     port(
      X:in std_logic;
      Cin: in std_logic;
      S: out std_logic;
      Cout:out std_logic);
  end component;

You want unsigned array values in inc6:

entity Inc6 is
  port( 
        X:in unsigned (5 downto 0);
        Y:out unsigned (5 downto 0));

architecture behaviour of Inc6 is
  signal C: unsigned (4 downto 0);

And indexed array elements as actuals connected to scalar formals:

begin
  I0: IncStage0
    port map(X=>X(0), S=>Y(0), Cout=>C(0));
  I1: IncStageI
    port map(X=>X(1), S=>Y(1), Cout=>C(1),Cin=>C(0));
  I2: IncStageI
    port map(X=>X(2), S=>Y(2), Cout=>C(2),Cin=>C(1));
  I3: IncStageI
    port map(X=>X(3), S=>Y(3), Cout=>C(3),Cin=>C(2));
  I4: IncStageI
    port map(X=>X(4), S=>Y(4), Cout=>C(4),Cin=>C(3));
  I5: IncStageI
    port map(X=>X(5), S=>Y(5), Cout=> open,Cin=>C(4));

And this leaves TBinc6 as you originally displayed it using unsigned and to_unsigned without error.

And don't forget to change the time specification for delay in incStage0:

architecture behaviour of IncStage0 is
begin
  S <= not X after 1 ns;

After which you can generate a wave form that shows identically to the exercise handout.

You've had more that 99 percent of the answer before running into the difference between array type and scalar types and their values. The circumlocution giving you snippets allows students taking the course to claim their work is their own. Learning and understanding, instead of simply copying.

Answer 2

What the question seems to be getting at, is that while you can use a general purpose adder (A + B + carry) to perform an increment, there are certain simplifications if you only need (A + 1) or (A + carry).

It appears to assume you have already been taught basic digital logic, gates, half adders and full adders. If not, this information is easily found.

So start by drawing out the "Full Adder" circuit for each bit. In Step (e), show what the simplifications are (at the gate level) when you simplify a 6 bit adder from (A + B + carry) to (A + carry).

The remaining steps will let you see if the simplified circuit is actually any faster. Looks like a good exercise in using the tools to do something really basic.