vhdl subtract std_logic_vector

Question

I am trying to substract 2 std logic vector and get error

p2 <= p1(11 downto 0)- idata(11 downto 0);

Error (10327): VHDL error at sub.vhd(32): can't determine definition of operator ""-"" -- found 0 possible definitions

I already tried to add use IEEE.std_logic_signed.all or use IEEE.std_logic_unsigned.all or both and already tried p2 <= std_logic_vector(unsigned(p1(11 downto 0)) - unsigned(idata(11 downto 0)));

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use IEEE.std_logic_signed.all;
--use IEEE.std_logic_unsigned.all;

entity sub is 

port (  
    clk         : in    std_logic;
    rst         : in    std_logic;
    --en            : in    std_logic;  
    idata    : in    std_logic_vector (11 downto 0);
    odata    : out  std_logic_vector (11 downto 0)  
);
end sub;

architecture beh of sub is
signal p1,p2 :std_logic_vector (11 downto 0);
begin
    process (clk, rst) 
        begin
            if (rst = '1') then
                odata  <= "000000000000";
            elsif (rising_edge (clk)) then  
                    p1 <= idata;
                    p2 <= p1(11 downto 0)- idata(11 downto 0);
                    --p2 <= std_logic_vector(unsigned(p1(11 downto 0)) - unsigned(idata(11 downto 0)));

            end if;             
    end process;
    odata<=p2;
end beh;

Morten Zilmer Morten Zilmer · Accepted Answer · 2015-12-02T08:39:19

The std_logic_vector type is just an array of std_logic, and does not by itself have any numerical interpretation, thus the error when trying to apply numeric operations like minus (-).

Don't use the Synopsys non-standard std_logic_signed/unsigned/arith packages.

VHDL-2002: use the unsigned type in the standard ieee.numeric_std package to convert a std_logic_vector to a unsigned representation, which allows use of numeric operations like minus. Code like:

use ieee.numeric_std.all;
...
p2 <= std_logic_vector(unsigned(p1(11 downto 0)) - unsigned(idata(11 downto 0)));

VHDL-2008: use the standard ieee.numeric_std_unsigned package to convert a std_logic_vector to a unsigned representation, which allows use of numeric operations like minus. Code like:

use ieee.numeric_std_unsigned.all;
...
p2 <= p1(11 downto 0) - idata(11 downto 0);

Btw. check out this search for similar issues.

vhdl subtract std_logic_vector

1 Answers