VHDL package and std_logic_vector

Question

I'm trying do declare a type to use in the port but i'm with a problem if I do the following I get an error that STD_LOGIC_VECTOR isn't declared

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- Custom types --
package Common  is
    type Mem_in is array (2**6 to 0) of STD_LOGIC_VECTOR (11 downto 0); 
    type DinDout is range 11 downto 0;
end package Common ;
-- Use Custom Type
use work.Common.all;

entity MUX is

    Port (
        D       :   in Mem_in;
        Q       :   out DinDout;
        SEL     :   in  STD_LOGIC_VECTOR (11 downto 0)
        );
end MUX;

Why can't I use STD_LOGIC_VECTOR? If I change it to DinDout I get another problem down the line in the architecture: to_integer is not declared; indexed name is not a dindout.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- Custom types --
package Common  is
    type Mem_in is array (2**6 to 0) of STD_LOGIC_VECTOR (11 downto 0); 
    type DinDout is range 11 downto 0;
end package Common ;

And the entity using package Common:

-- Use Custom Type
use work.Common.all;

entity MUX is

    Port (
        D       :   in Mem_in;
        Q       :   out DinDout;
        SEL     :   in  DinDout
        );
end MUX;

architecture Arc of MUX is
begin
    Q <= D(to_integer(unsigned(SEL)));
end Arc;

how can I add STD_logic_vector to my package OR solve these two errors: to_integer is not declared; indexed name is not a dindout?

thanks

In addition to the MUX entity declaration missing context items in the preceding context clause your Mem_in array type has 2**6 + 1 (2**6 downto 0) elements which is going the same number of distinct indexes not 2**DinDout'length causing a constraint violations for some values of SEL. Your memory size should be a power of 2 matching the length of SEL. It seems unusual to provide a port with so many 'bits' (2**6+1 * 12 - the length of a memory element or 780. This memory read MUX that should likely be located with the actual for D particularly for block memory. — user1155120
Type DinDout is an abstract numerical type with a value range of 11 downto 0, while D(to_integer(unsigned(SEL))) is an indexed element of D which is an array of std_logic_vectors with an index range of 11 downto 0. They are different types. Note your accepted answer did not address ...OR solve these two errors:...indexed name is not a dindout? You have multiple errors. — user1155120

Andreas Bombe Andreas Bombe · Accepted Answer · 2017-09-28T18:26:35

You have two library units in one file (if it is a single file you have quoted). While I am not sure what happens, I guess it restarts the context with every unit.

That would mean you have to repeat library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; before use work.Common.all;.

Also 2**6 to 0 is a null range, that should be 0 to 2**6 or 2**6 downto 0.

VHDL package and std_logic_vector

1 Answers