System Verilog Bus Routing

2
votes

In system verilog, I know you can route a partial bus with array[15:8] as a way to split lanes. Is there any way to do this in a non continuous way. For example, lane 2,3,8,9 .

2
verilogsystem-verilogmodelsim

2 Answers

2
votes

You can connect the in any way:

For example:

 assign a[0] = b[2];
 assign a[1] = b[3];
 assign a[3:2] = b[9:8];
2
votes

Alternative to Enze Chi way is to use concatenation:

wire [3:0] a;
assign a = {b[9:8],b[3],b[2]};