I'm trying to implement Macro to expand Verilog Bus as Vim - Macro to expand verilog bus and this is really working good for one variable.
But I've got the problem because I want to implement multiple bus as the below
Source:
{test[13:10],thisistest[3:0],BUS[2:1]}
Result:
test[13]
test[12]
test[11]
test[10]
thisistest[3]
thisistest[2]
thisistest[1]
thisistest[0]
BUS[2]
BUS[1]
What I tried to do : I made similar function as
fun! split()
let line = getline('.')
let result = []
let list = split(line, ",")
let length = len(list)
for i in length
call ExpandIt(list[length])
endfor
endf
fun! ExpandIt()
let pat = '^\(.*\)\[\(\d\+\):\(\d\+\)\]\s*$'
let line = getline('.')
let lnr = line('.')
if line !~ pat
return
endif
let exestr = substitute(line,pat,'range(\2,\3,-1)','g')
let text = substitute(line,pat,'\1','g')
exec 'let range='.exestr
let result = []
for i in range
call add(result, text.'['.i.']')
endfor
call append(lnr, result)
exec lnr'.d'
endf
nnoremap <F6> :call split()<cr>
Could you please let me know what am I supposed to do to go with right way?