system verilog slicing arrays

Question

I am still not sure how the array slicing works in System Verilog?

For example, let's say that I have a packed 2D array.

localparam [0:2][4:0] TEMP = {5'd4,5'd9,5'd20};

So my array has three rows and each row is a 5-bit number.

So, when I am trying to do something like this, it doesn't quite work !!!

logic [1:0] arr;

assign arr = TEMP[0][1:0]

How come this doesn't work? The compiler doesn't complain, but the simulation shows all 'X !!

Here I am including the module that has the issue:

module slice_issue ();

// clock and reset 
reg board_resetl;
reg tb_clkh;
parameter CLK_PER  = 4;


always #(CLK_PER/2) tb_clkh = ~ tb_clkh;

initial begin: main_process
  board_resetl = 0;
  tb_clkh = 0;

  #100 
  @(posedge tb_clkh);  
  board_resetl = 1;

 end



localparam logic [4:0] PARAM_1 = 14;
localparam logic [4:0] PARAM_2 = 18;
localparam logic [4:0] PARAM_3 = 26;

localparam [0:2] [4:0] CAND_MODE_LIST = {PARAM_1, PARAM_2, PARAM_3};

logic [1:0] temp;
logic [4:0] temp2;

logic [1:0] in_pred_mode;

logic [4:0] cnt_reg; 

always @ (posedge tb_clkh or negedge board_resetl) 
    begin  
       if (~board_resetl) begin 
          in_pred_mode <= 0; 
          cnt_reg  <= 0;
       end else  
          cnt_reg  <= cnt_reg + 1; 
       if (cnt_reg == 31) begin
          in_pred_mode <= $urandom_range(0, 1); 
       end
    end

// bad
assign temp  = CAND_MODE_LIST[in_pred_mode][1:0];

// good 
assign temp2  = CAND_MODE_LIST[in_pred_mode];

endmodule

Can you explain what you think the compiler should complain about? Your code looks fine to me. TEMP is a 15 bit parameter and you've assigned with a 15-bit concatenation. Since it is a packed array, the size does not even have to match. The implicit parameter type is logic so there could be a race at time 0 before arr assigned; it could still be 'x. You need to show a complete self-contained example. — dave_59
I don't know why I got a minus on my question. There is nothing else in my code. that is simply it. Just for a test I put that in a module, and there is not even a sequential process in my code. This simply doesn't work with during simulation. And I was just wondering why? Again there is no warnings or anything, but the result is 'x all the way — Rudy01
The code you have shown so far will not compile by itself - it is not inside a module or interface. How do you know arr is 'x? Where is the $display — dave_59

Morgan Morgan · Accepted Answer · 2015-06-09T06:52:26

A self contained example could be :

module tb;

  localparam [0:2][4:0] TEMP = {5'd4,5'd9,5'd20};
  logic [1:0] arr;

  assign arr = TEMP[0][1:0];

  initial begin
    $display("arr : %b", arr);
    #1ps;
    $display(TEMP[0]);
    $display(TEMP[1]);
    $display(TEMP[2]);
    $display("arr : %b", arr);
  end

endmodule

For me this (correctly) outputs:

# KERNEL: arr : 00
# KERNEL:  4
# KERNEL:  9
# KERNEL: 20
# KERNEL: arr : 00

This does not show the error condition from the question, unless the question adds more information, the exact reason for the error can not be determined.

example on EDA Playground

system verilog slicing arrays

2 Answers