System Verilog number multiplication?

0
votes

How can I multiply by -1 in system Verilog? Inside an ALU?

I tried:

 logic [DPWIDTH-1:0] alu_result;
 always_comb
     case (alusel)
         ALU_REV: alu_result = alu_a * (-1);
     endcase

But for some reason it doesn't work as expected.

2
verilogsystem-verilog
Please explain what you were expecting versus what you actually saw. It also helps to show declarations of all variables involved . - dave_59
keep in mind that alu_result is not signed in our declaration. - Serge

2 Answers

0
votes

The first answer in my mind is:

alu_result = -alu_a;

But if you want to use multiplication you must use signed variables:

localparam logic signed [DPWIDTH/2-1:0] NEGATIVE_ONE_C = -1;
logic signed [DPWIDTH-1:0] alu_result;

always_comb begin
  case (alusel)
    ALU_REV: begin
      alu_result = signed'(alu_a) * NEGATIVE_ONE_C;
    end
  endcase
end

Instead of typecasting alu_a you should change its declaration, too. Also, note the size of NEGATIVE_ONE_C.

-1
votes

If you want just to store the variables as their negative in ALU. Then you can also use 2's complement method too store in bits. number = -number; or number = 'number + 1'b1;