Present State of Random Number Generator in System Verilog

3
votes

How we can get the present state or present seed of Random number generator in system verilog??

1
verilogverificationregister-transfer-levelsystem-verilog

1 Answers

3
votes

Use get_randstate(), which is defined as

function string get_randstate();

From the SystemVerilog 2012 language spec:

The get_randstate() method returns a copy of the internal state of the RNG associated with the given object. The RNG state is a string of unspecified length and format. The length and contents of the string are implementation dependent.

Note that SystemVerilog will create a separate RNG for each thread and object, so you'll see different results from different objects.

Example:

t1 = new;
t2 = new;
$display(t1.get_randstate());
$display(t2.get_randstate());

Sample output from Incisive:

svseed=1 ; 5864a323c57f14c ; 
svseed=1 ; bbfc1b9e8eb663ae ;