Equivalent of System verilog packaged input output in verilog file

Question

I am having one system verilog file as stated below

module bist_wrapper 
(

input wire clk_mbist;
output wire BIST_GO_ts3,
  output  mbist_hsm_p::mbist_in_hsm_sysram_t  mbist_in,
  input   mbist_hsm_p::mbist_out_hsm_sysram_t mbist_out
);

 assign mbist_in.clk_mbist = clk_mbist;
 assign BIST_GO_ts3 = mbist_out.BIST_GO_ts3;
endmodule

I need to create verilog file which should be equivalent to system verilog file , but how to handle system verilog packaged input output as verilog input output

Is the below file the right one ?? Do I need to declare the "wire" here ?



module bist_wrapper (
clk_mbist, BIST_GO_ts3,mbist_in, mbist_out);

input clk_mbist;
output BIST_GO_ts3;

output  mbist_hsm_p::mbist_in_hsm_sysram_t  mbist_in;
  input   mbist_hsm_p::mbist_out_hsm_sysram_t mbist_out;

assign mbist_in.clk_mbist = clk_mbist;
 assign BIST_GO_ts3 = mbist_out.BIST_GO_ts3;
endmodule

Which version of verilog do you target? for example, v95 does not have structs, typedefs and other stuff. — Serge
Hi Please find the package ``` package mbist_hsm_p; typedef struct packed { mbist_in_hsm_pkram_t pkram; mbist_in_hsm_sysram_t sysram; } mbist_in_hsm_t; typedef struct packed { mbist_out_hsm_pkram_t pkram; mbist_out_hsm_sysram_t sysram; } mbist_out_hsm_t; endpackage ``` — kshitij kulshreshtha

Serge Serge · Accepted Answer · 2019-11-24T03:57:41

You cannot use packages or import notations within regular verilog. So, your example will not work with verilog.

The usual way for sharing types and parameters in verilog is to include them inside module scopes. For example,

file types.vh

typedef reg[3:0] out_t;

file b.v

module b(in,out);
    `include "types.vh"
   output out_t out;
    ...
endmodle

So, you need to put the contents of your package in a separate file and include it before var declarations.

Equivalent of System verilog packaged input output in verilog file

1 Answers